Lines Matching +full:0 +full:xf004
42 { 249600000, 2020000000, 0 },
46 { 864000000, 1056000000, 0 },
51 .l = 0x3e,
52 .alpha = 0x8000,
53 .config_ctl_val = 0x20485699,
54 .config_ctl_hi_val = 0x00182261,
55 .config_ctl_hi1_val = 0x32aa299c,
56 .user_ctl_val = 0x00008400,
57 .user_ctl_hi_val = 0x00000805,
61 .offset = 0x0,
78 { 0x1, 2 },
83 .offset = 0x0,
101 { 0x2, 3 },
106 .offset = 0x0,
125 .l = 0x1f,
126 .alpha = 0x4000,
127 .config_ctl_val = 0x20485699,
128 .config_ctl_hi_val = 0x00182261,
129 .config_ctl_hi1_val = 0x32aa299c,
130 .user_ctl_val = 0x00000400,
131 .user_ctl_hi_val = 0x00000805,
135 .offset = 0x1000,
152 { 0x1, 2 },
157 .offset = 0x1000,
176 .l = 0x32,
177 .alpha = 0x0,
178 .config_ctl_val = 0x90008820,
179 .config_ctl_hi_val = 0x00890263,
180 .config_ctl_hi1_val = 0x00000247,
181 .user_ctl_val = 0x00000400,
182 .user_ctl_hi_val = 0x00400000,
186 .offset = 0x2000,
203 { 0x1, 2 },
208 .offset = 0x2000,
227 .l = 0x1f,
228 .alpha = 0x4000,
229 .config_ctl_val = 0x20485699,
230 .config_ctl_hi_val = 0x00182261,
231 .config_ctl_hi1_val = 0x32aa299c,
232 .user_ctl_val = 0x00000400,
233 .user_ctl_hi_val = 0x00000805,
237 .offset = 0x3000,
254 { 0x1, 2 },
259 .offset = 0x3000,
278 .l = 0x24,
279 .alpha = 0x7555,
280 .config_ctl_val = 0x20485699,
281 .config_ctl_hi_val = 0x00182261,
282 .config_ctl_hi1_val = 0x32aa299c,
283 .user_ctl_val = 0x00000400,
284 .user_ctl_hi_val = 0x00000805,
288 .offset = 0x4000,
305 { 0x1, 2 },
310 .offset = 0x4000,
328 { P_BI_TCXO, 0 },
342 { P_BI_TCXO, 0 },
354 { P_BI_TCXO, 0 },
366 { P_BI_TCXO, 0 },
384 { P_BI_TCXO, 0 },
402 { P_BI_TCXO, 0 },
414 { P_BI_TCXO, 0 },
426 { P_BI_TCXO, 0 },
440 F(19200000, P_BI_TCXO, 1, 0, 0),
441 F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
442 F(410000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
443 F(460000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
444 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
445 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
450 .cmd_rcgr = 0xa004,
451 .mnd_width = 0,
465 F(19200000, P_BI_TCXO, 1, 0, 0),
466 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
467 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
468 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
469 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
474 .cmd_rcgr = 0x13014,
475 .mnd_width = 0,
489 F(19200000, P_BI_TCXO, 1, 0, 0),
490 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
491 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
492 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
497 .cmd_rcgr = 0x10004,
512 .cmd_rcgr = 0x11004,
527 F(19200000, P_BI_TCXO, 1, 0, 0),
528 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
529 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
534 .cmd_rcgr = 0xc054,
535 .mnd_width = 0,
549 .cmd_rcgr = 0x16004,
550 .mnd_width = 0,
564 F(19200000, P_BI_TCXO, 1, 0, 0),
565 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
570 .cmd_rcgr = 0x9004,
571 .mnd_width = 0,
585 .cmd_rcgr = 0x9028,
586 .mnd_width = 0,
600 .cmd_rcgr = 0x904c,
601 .mnd_width = 0,
615 F(19200000, P_BI_TCXO, 1, 0, 0),
616 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
617 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
618 F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 6, 0, 0),
619 F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0),
624 .cmd_rcgr = 0xa02c,
625 .mnd_width = 0,
639 F(19200000, P_BI_TCXO, 1, 0, 0),
640 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
641 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
642 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
647 .cmd_rcgr = 0xf014,
648 .mnd_width = 0,
664 F(64000000, P_CAM_CC_PLL2_OUT_MAIN, 15, 0, 0),
669 .cmd_rcgr = 0x8004,
684 .cmd_rcgr = 0x8024,
699 .cmd_rcgr = 0x8044,
714 .cmd_rcgr = 0x8064,
729 F(19200000, P_BI_TCXO, 1, 0, 0),
730 F(300000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
731 F(410000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
732 F(460000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
733 F(600000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
734 F(700000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
739 .cmd_rcgr = 0xb004,
740 .mnd_width = 0,
754 F(19200000, P_BI_TCXO, 1, 0, 0),
755 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
760 .cmd_rcgr = 0xa048,
761 .mnd_width = 0,
775 F(19200000, P_BI_TCXO, 1, 0, 0),
776 F(350000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
777 F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
778 F(548000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
779 F(630000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
784 .cmd_rcgr = 0xc004,
785 .mnd_width = 0,
799 .cmd_rcgr = 0xc02c,
800 .mnd_width = 0,
814 .cmd_rcgr = 0xd004,
815 .mnd_width = 0,
829 .cmd_rcgr = 0xd024,
830 .mnd_width = 0,
844 .halt_reg = 0xa060,
847 .enable_reg = 0xa060,
848 .enable_mask = BIT(0),
862 .halt_reg = 0xa044,
865 .enable_reg = 0xa044,
866 .enable_mask = BIT(0),
880 .halt_reg = 0xa01c,
883 .enable_reg = 0xa01c,
884 .enable_mask = BIT(0),
898 .halt_reg = 0x13034,
901 .enable_reg = 0x13034,
902 .enable_mask = BIT(0),
911 .halt_reg = 0x1302c,
914 .enable_reg = 0x1302c,
915 .enable_mask = BIT(0),
929 .halt_reg = 0x1300c,
932 .enable_reg = 0x1300c,
933 .enable_mask = BIT(0),
942 .halt_reg = 0x13004,
945 .enable_reg = 0x13004,
946 .enable_mask = BIT(0),
955 .halt_reg = 0x1001c,
958 .enable_reg = 0x1001c,
959 .enable_mask = BIT(0),
973 .halt_reg = 0x1101c,
976 .enable_reg = 0x1101c,
977 .enable_mask = BIT(0),
991 .halt_reg = 0x1401c,
994 .enable_reg = 0x1401c,
995 .enable_mask = BIT(0),
1009 .halt_reg = 0x12004,
1012 .enable_reg = 0x12004,
1013 .enable_mask = BIT(0),
1027 .halt_reg = 0x16020,
1030 .enable_reg = 0x16020,
1031 .enable_mask = BIT(0),
1045 .halt_reg = 0x1601c,
1048 .enable_reg = 0x1601c,
1049 .enable_mask = BIT(0),
1063 .halt_reg = 0x901c,
1066 .enable_reg = 0x901c,
1067 .enable_mask = BIT(0),
1081 .halt_reg = 0x9040,
1084 .enable_reg = 0x9040,
1085 .enable_mask = BIT(0),
1099 .halt_reg = 0x9064,
1102 .enable_reg = 0x9064,
1103 .enable_mask = BIT(0),
1117 .halt_reg = 0x9020,
1120 .enable_reg = 0x9020,
1121 .enable_mask = BIT(0),
1135 .halt_reg = 0x9044,
1138 .enable_reg = 0x9044,
1139 .enable_mask = BIT(0),
1153 .halt_reg = 0x9068,
1156 .enable_reg = 0x9068,
1157 .enable_mask = BIT(0),
1171 .halt_reg = 0xf004,
1174 .enable_reg = 0xf004,
1175 .enable_mask = BIT(0),
1184 .halt_reg = 0xf02c,
1187 .enable_reg = 0xf02c,
1188 .enable_mask = BIT(0),
1202 .halt_reg = 0xf008,
1205 .enable_reg = 0xf008,
1206 .enable_mask = BIT(0),
1215 .halt_reg = 0xf00c,
1218 .enable_reg = 0xf00c,
1219 .enable_mask = BIT(0),
1228 .halt_reg = 0x801c,
1231 .enable_reg = 0x801c,
1232 .enable_mask = BIT(0),
1246 .halt_reg = 0x803c,
1249 .enable_reg = 0x803c,
1250 .enable_mask = BIT(0),
1264 .halt_reg = 0x805c,
1267 .enable_reg = 0x805c,
1268 .enable_mask = BIT(0),
1282 .halt_reg = 0x807c,
1285 .enable_reg = 0x807c,
1286 .enable_mask = BIT(0),
1300 .halt_reg = 0xb030,
1303 .enable_reg = 0xb030,
1304 .enable_mask = BIT(0),
1318 .halt_reg = 0xb02c,
1321 .enable_reg = 0xb02c,
1322 .enable_mask = BIT(0),
1336 .halt_reg = 0xb01c,
1339 .enable_reg = 0xb01c,
1340 .enable_mask = BIT(0),
1354 .halt_reg = 0x14018,
1357 .enable_reg = 0x14018,
1358 .enable_mask = BIT(0),
1367 .halt_reg = 0xf034,
1370 .enable_reg = 0xf034,
1371 .enable_mask = BIT(0),
1380 .halt_reg = 0xc070,
1383 .enable_reg = 0xc070,
1384 .enable_mask = BIT(0),
1398 .halt_reg = 0xc01c,
1401 .enable_reg = 0xc01c,
1402 .enable_mask = BIT(0),
1416 .halt_reg = 0xc06c,
1419 .enable_reg = 0xc06c,
1420 .enable_mask = BIT(0),
1434 .halt_reg = 0xc044,
1437 .enable_reg = 0xc044,
1438 .enable_mask = BIT(0),
1452 .halt_reg = 0xd048,
1455 .enable_reg = 0xd048,
1456 .enable_mask = BIT(0),
1470 .halt_reg = 0xd01c,
1473 .enable_reg = 0xd01c,
1474 .enable_mask = BIT(0),
1488 .halt_reg = 0xd044,
1491 .enable_reg = 0xd044,
1492 .enable_mask = BIT(0),
1506 .halt_reg = 0xd03c,
1509 .enable_reg = 0xd03c,
1510 .enable_mask = BIT(0),
1524 .gdscr = 0x14004,
1525 .en_rest_wait_val = 0x2,
1526 .en_few_wait_val = 0x2,
1527 .clk_dis_wait_val = 0xf,
1615 [CAM_CC_BPS_BCR] = { 0xa000 },
1616 [CAM_CC_CAMNOC_BCR] = { 0x13000 },
1617 [CAM_CC_CAMSS_TOP_BCR] = { 0x14000 },
1618 [CAM_CC_CCI_0_BCR] = { 0x10000 },
1619 [CAM_CC_CCI_1_BCR] = { 0x11000 },
1620 [CAM_CC_CPAS_BCR] = { 0x12000 },
1621 [CAM_CC_CRE_BCR] = { 0x16000 },
1622 [CAM_CC_CSI0PHY_BCR] = { 0x9000 },
1623 [CAM_CC_CSI1PHY_BCR] = { 0x9024 },
1624 [CAM_CC_CSI2PHY_BCR] = { 0x9048 },
1625 [CAM_CC_ICP_BCR] = { 0xf000 },
1626 [CAM_CC_MCLK0_BCR] = { 0x8000 },
1627 [CAM_CC_MCLK1_BCR] = { 0x8020 },
1628 [CAM_CC_MCLK2_BCR] = { 0x8040 },
1629 [CAM_CC_MCLK3_BCR] = { 0x8060 },
1630 [CAM_CC_OPE_0_BCR] = { 0xb000 },
1631 [CAM_CC_TFE_0_BCR] = { 0xc000 },
1632 [CAM_CC_TFE_1_BCR] = { 0xd000 },
1639 .max_register = 0x16024,