Lines Matching +full:0 +full:x9038

30 	.offset = 0x0,
45 { 0x0, 1 },
46 { 0x1, 2 },
51 .offset = 0x0,
68 .offset = 0x1000,
83 .offset = 0x1000,
100 .offset = 0x2000,
115 .offset = 0x2000,
132 .offset = 0x3000,
147 .offset = 0x3000,
164 { P_BI_TCXO, 0 },
180 F(19200000, P_BI_TCXO, 1, 0, 0),
181 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
182 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
183 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
184 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
185 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
199 .cmd_rcgr = 0x600c,
200 .mnd_width = 0,
214 F(19200000, P_BI_TCXO, 1, 0, 0),
215 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
216 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
217 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
222 .cmd_rcgr = 0xb0d8,
236 F(19200000, P_BI_TCXO, 1, 0, 0),
237 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
242 .cmd_rcgr = 0x9060,
243 .mnd_width = 0,
256 F(19200000, P_BI_TCXO, 1, 0, 0),
257 F(240000000, P_CAM_CC_PLL2_OUT_EVEN, 2, 0, 0),
258 F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0),
263 .cmd_rcgr = 0x5004,
264 .mnd_width = 0,
278 .cmd_rcgr = 0x5028,
279 .mnd_width = 0,
293 .cmd_rcgr = 0x504c,
294 .mnd_width = 0,
308 .cmd_rcgr = 0x5070,
309 .mnd_width = 0,
323 F(19200000, P_BI_TCXO, 1, 0, 0),
324 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
325 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
326 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
327 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
328 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
333 .cmd_rcgr = 0x6038,
334 .mnd_width = 0,
347 F(19200000, P_BI_TCXO, 1, 0, 0),
348 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
349 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
350 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
351 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
356 .cmd_rcgr = 0xb0b0,
357 .mnd_width = 0,
370 F(19200000, P_BI_TCXO, 1, 0, 0),
371 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
372 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
373 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
374 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
379 .cmd_rcgr = 0xb088,
380 .mnd_width = 0,
393 F(19200000, P_BI_TCXO, 1, 0, 0),
394 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
395 F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0),
396 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
397 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
398 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
403 .cmd_rcgr = 0x900c,
404 .mnd_width = 0,
418 F(19200000, P_BI_TCXO, 1, 0, 0),
419 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
420 F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
421 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
426 .cmd_rcgr = 0x9038,
427 .mnd_width = 0,
440 .cmd_rcgr = 0xa00c,
441 .mnd_width = 0,
455 .cmd_rcgr = 0xa030,
456 .mnd_width = 0,
469 .cmd_rcgr = 0xb004,
470 .mnd_width = 0,
484 .cmd_rcgr = 0xb024,
485 .mnd_width = 0,
498 F(19200000, P_BI_TCXO, 1, 0, 0),
499 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
500 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
501 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
502 F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
503 F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),
504 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
509 .cmd_rcgr = 0x700c,
510 .mnd_width = 0,
524 .cmd_rcgr = 0x800c,
525 .mnd_width = 0,
539 .cmd_rcgr = 0xb04c,
540 .mnd_width = 0,
554 F(19200000, P_BI_TCXO, 1, 0, 0),
555 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
556 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
557 F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0),
558 F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0),
559 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
564 .cmd_rcgr = 0xb0f8,
565 .mnd_width = 0,
579 F(19200000, P_BI_TCXO, 1, 0, 0),
582 F(34285714, P_CAM_CC_PLL2_OUT_EVEN, 14, 0, 0),
587 .cmd_rcgr = 0x4004,
602 .cmd_rcgr = 0x4024,
617 .cmd_rcgr = 0x4044,
632 .cmd_rcgr = 0x4064,
647 F(19200000, P_BI_TCXO, 1, 0, 0),
648 F(60000000, P_CAM_CC_PLL0_OUT_EVEN, 10, 0, 0),
649 F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0),
650 F(73846154, P_CAM_CC_PLL2_OUT_EVEN, 6.5, 0, 0),
651 F(80000000, P_CAM_CC_PLL2_OUT_EVEN, 6, 0, 0),
656 .cmd_rcgr = 0x6054,
657 .mnd_width = 0,
671 .halt_reg = 0x606c,
674 .enable_reg = 0x606c,
675 .enable_mask = BIT(0),
689 .halt_reg = 0x6050,
692 .enable_reg = 0x6050,
693 .enable_mask = BIT(0),
707 .halt_reg = 0x6034,
710 .enable_reg = 0x6034,
711 .enable_mask = BIT(0),
720 .halt_reg = 0x6024,
723 .enable_reg = 0x6024,
724 .enable_mask = BIT(0),
738 .halt_reg = 0xb12c,
741 .enable_reg = 0xb12c,
742 .enable_mask = BIT(0),
751 .halt_reg = 0xb124,
754 .enable_reg = 0xb124,
755 .enable_mask = BIT(0),
764 .halt_reg = 0xb0f0,
767 .enable_reg = 0xb0f0,
768 .enable_mask = BIT(0),
782 .halt_reg = 0xb11c,
785 .enable_reg = 0xb11c,
786 .enable_mask = BIT(0),
800 .halt_reg = 0x501c,
803 .enable_reg = 0x501c,
804 .enable_mask = BIT(0),
818 .halt_reg = 0x5040,
821 .enable_reg = 0x5040,
822 .enable_mask = BIT(0),
836 .halt_reg = 0x5064,
839 .enable_reg = 0x5064,
840 .enable_mask = BIT(0),
854 .halt_reg = 0x5088,
857 .enable_reg = 0x5088,
858 .enable_mask = BIT(0),
872 .halt_reg = 0x5020,
875 .enable_reg = 0x5020,
876 .enable_mask = BIT(0),
890 .halt_reg = 0x5044,
893 .enable_reg = 0x5044,
894 .enable_mask = BIT(0),
908 .halt_reg = 0x5068,
911 .enable_reg = 0x5068,
912 .enable_mask = BIT(0),
926 .halt_reg = 0x508c,
929 .enable_reg = 0x508c,
930 .enable_mask = BIT(0),
944 .halt_reg = 0xb0c8,
947 .enable_reg = 0xb0c8,
948 .enable_mask = BIT(0),
962 .halt_reg = 0xb0d0,
965 .enable_reg = 0xb0d0,
966 .enable_mask = BIT(0),
979 .halt_reg = 0xb084,
982 .enable_reg = 0xb084,
983 .enable_mask = BIT(0),
992 .halt_reg = 0xb078,
995 .enable_reg = 0xb078,
996 .enable_mask = BIT(0),
1005 .halt_reg = 0xb0a0,
1008 .enable_reg = 0xb0a0,
1009 .enable_mask = BIT(0),
1023 .halt_reg = 0xb07c,
1026 .enable_reg = 0xb07c,
1027 .enable_mask = BIT(0),
1036 .halt_reg = 0xb080,
1039 .enable_reg = 0xb080,
1040 .enable_mask = BIT(0),
1049 .halt_reg = 0x907c,
1052 .enable_reg = 0x907c,
1053 .enable_mask = BIT(0),
1062 .halt_reg = 0x9024,
1065 .enable_reg = 0x9024,
1066 .enable_mask = BIT(0),
1080 .halt_reg = 0x9078,
1083 .enable_reg = 0x9078,
1084 .enable_mask = BIT(0),
1098 .halt_reg = 0x9050,
1101 .enable_reg = 0x9050,
1102 .enable_mask = BIT(0),
1116 .halt_reg = 0x9034,
1119 .enable_reg = 0x9034,
1120 .enable_mask = BIT(0),
1133 .halt_reg = 0xa054,
1136 .enable_reg = 0xa054,
1137 .enable_mask = BIT(0),
1146 .halt_reg = 0xa024,
1149 .enable_reg = 0xa024,
1150 .enable_mask = BIT(0),
1164 .halt_reg = 0xa050,
1167 .enable_reg = 0xa050,
1168 .enable_mask = BIT(0),
1182 .halt_reg = 0xa048,
1185 .enable_reg = 0xa048,
1186 .enable_mask = BIT(0),
1200 .halt_reg = 0xa02c,
1203 .enable_reg = 0xa02c,
1204 .enable_mask = BIT(0),
1217 .halt_reg = 0xb01c,
1220 .enable_reg = 0xb01c,
1221 .enable_mask = BIT(0),
1235 .halt_reg = 0xb044,
1238 .enable_reg = 0xb044,
1239 .enable_mask = BIT(0),
1253 .halt_reg = 0xb03c,
1256 .enable_reg = 0xb03c,
1257 .enable_mask = BIT(0),
1271 .halt_reg = 0x703c,
1274 .enable_reg = 0x703c,
1275 .enable_mask = BIT(0),
1289 .halt_reg = 0x7038,
1292 .enable_reg = 0x7038,
1293 .enable_mask = BIT(0),
1307 .halt_reg = 0x7034,
1310 .enable_reg = 0x7034,
1311 .enable_mask = BIT(0),
1320 .halt_reg = 0x7024,
1323 .enable_reg = 0x7024,
1324 .enable_mask = BIT(0),
1338 .halt_reg = 0x803c,
1341 .enable_reg = 0x803c,
1342 .enable_mask = BIT(0),
1356 .halt_reg = 0x8038,
1359 .enable_reg = 0x8038,
1360 .enable_mask = BIT(0),
1374 .halt_reg = 0x8034,
1377 .enable_reg = 0x8034,
1378 .enable_mask = BIT(0),
1387 .halt_reg = 0x8024,
1390 .enable_reg = 0x8024,
1391 .enable_mask = BIT(0),
1405 .halt_reg = 0xb064,
1408 .enable_reg = 0xb064,
1409 .enable_mask = BIT(0),
1423 .halt_reg = 0xb110,
1426 .enable_reg = 0xb110,
1427 .enable_mask = BIT(0),
1441 .halt_reg = 0x401c,
1444 .enable_reg = 0x401c,
1445 .enable_mask = BIT(0),
1459 .halt_reg = 0x403c,
1462 .enable_reg = 0x403c,
1463 .enable_mask = BIT(0),
1477 .halt_reg = 0x405c,
1480 .enable_reg = 0x405c,
1481 .enable_mask = BIT(0),
1495 .halt_reg = 0x407c,
1498 .enable_reg = 0x407c,
1499 .enable_mask = BIT(0),
1513 .halt_reg = 0xb13c,
1516 .enable_reg = 0xb13c,
1517 .enable_mask = BIT(0),
1526 .halt_reg = 0xb0a8,
1529 .enable_reg = 0xb0a8,
1530 .enable_mask = BIT(0),
1541 .gdscr = 0x6004,
1550 .gdscr = 0x7004,
1559 .gdscr = 0x8004,
1568 .gdscr = 0x9004,
1578 .gdscr = 0xa004,
1588 .gdscr = 0xb134,
1697 .max_register = 0xd004,
1724 cam_cc_pll_config.l = 0x1f;
1725 cam_cc_pll_config.alpha = 0x4000;
1728 cam_cc_pll_config.l = 0x2a;
1729 cam_cc_pll_config.alpha = 0x1556;
1732 cam_cc_pll_config.l = 0x32;
1733 cam_cc_pll_config.alpha = 0x0;
1736 cam_cc_pll_config.l = 0x14;