Lines Matching +full:0 +full:x9038
35 { 600000000, 3300000000UL, 0 },
39 { 249600000, 2000000000UL, 0 },
44 .l = 0x1f,
45 .alpha = 0x4000,
46 .config_ctl_val = 0x20485699,
47 .config_ctl_hi_val = 0x00002067,
48 .test_ctl_val = 0x40000000,
49 .user_ctl_hi_val = 0x00004805,
50 .user_ctl_val = 0x00000001,
54 .offset = 0x0,
72 .l = 0x2a,
73 .alpha = 0x1555,
74 .config_ctl_val = 0x20485699,
75 .config_ctl_hi_val = 0x00002067,
76 .test_ctl_val = 0x40000000,
77 .user_ctl_hi_val = 0x00004805,
81 .offset = 0x1000,
99 .l = 0x64,
100 .config_ctl_val = 0x20000800,
101 .config_ctl_hi_val = 0x400003D2,
102 .test_ctl_val = 0x04000400,
103 .test_ctl_hi_val = 0x00004000,
104 .user_ctl_val = 0x0000030F,
108 .offset = 0x2000,
138 { 0x3, 4 },
143 .offset = 0x2000,
162 .l = 0x38,
163 .alpha = 0x4000,
164 .config_ctl_val = 0x20485699,
165 .config_ctl_hi_val = 0x00002067,
166 .test_ctl_val = 0x40000000,
167 .user_ctl_hi_val = 0x00004805,
171 .offset = 0x3000,
188 { P_BI_TCXO, 0 },
200 { P_BI_TCXO, 0 },
210 { P_BI_TCXO, 0 },
224 { P_BI_TCXO, 0 },
240 { P_BI_TCXO, 0 },
252 { P_BI_TCXO, 0 },
262 { P_BI_TCXO, 0 },
276 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
277 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
278 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
279 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
280 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
285 .cmd_rcgr = 0x6010,
286 .mnd_width = 0,
299 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
300 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
301 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
306 .cmd_rcgr = 0xb0d8,
320 .cmd_rcgr = 0xb14c,
334 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
335 F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0),
336 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
341 .cmd_rcgr = 0x9064,
342 .mnd_width = 0,
355 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
360 .cmd_rcgr = 0x5004,
361 .mnd_width = 0,
374 .cmd_rcgr = 0x5028,
375 .mnd_width = 0,
388 .cmd_rcgr = 0x504c,
389 .mnd_width = 0,
402 .cmd_rcgr = 0x5070,
403 .mnd_width = 0,
416 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
417 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
418 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
419 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
424 .cmd_rcgr = 0x603c,
425 .mnd_width = 0,
438 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
439 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
440 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
441 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
442 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
447 .cmd_rcgr = 0xb088,
448 .mnd_width = 0,
461 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
462 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
463 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
464 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
469 .cmd_rcgr = 0x9010,
470 .mnd_width = 0,
483 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
484 F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0),
485 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
486 F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0),
491 .cmd_rcgr = 0x903c,
492 .mnd_width = 0,
505 .cmd_rcgr = 0xa010,
506 .mnd_width = 0,
519 .cmd_rcgr = 0xa034,
520 .mnd_width = 0,
533 .cmd_rcgr = 0xb004,
534 .mnd_width = 0,
548 .cmd_rcgr = 0xb024,
549 .mnd_width = 0,
562 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
563 F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0),
564 F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0),
565 F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0),
566 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
571 .cmd_rcgr = 0x7010,
572 .mnd_width = 0,
585 F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0),
586 F(133333333, P_CAM_CC_PLL0_OUT_EVEN, 4.5, 0, 0),
587 F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0),
588 F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0),
589 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
594 .cmd_rcgr = 0xb04c,
595 .mnd_width = 0,
608 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
609 F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0),
610 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
611 F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0),
616 .cmd_rcgr = 0xb0f8,
617 .mnd_width = 0,
630 F(19200000, P_BI_TCXO, 1, 0, 0),
632 F(64000000, P_CAM_CC_PLL2_OUT_AUX, 7.5, 0, 0),
637 .cmd_rcgr = 0x4004,
651 .cmd_rcgr = 0x4024,
665 .cmd_rcgr = 0x4044,
679 .cmd_rcgr = 0x4064,
693 .cmd_rcgr = 0x4084,
707 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
712 .cmd_rcgr = 0x6058,
713 .mnd_width = 0,
727 .halt_reg = 0x6070,
730 .enable_reg = 0x6070,
731 .enable_mask = BIT(0),
745 .halt_reg = 0x6054,
748 .enable_reg = 0x6054,
749 .enable_mask = BIT(0),
763 .halt_reg = 0x6038,
766 .enable_reg = 0x6038,
767 .enable_mask = BIT(0),
776 .halt_reg = 0x6028,
779 .enable_reg = 0x6028,
780 .enable_mask = BIT(0),
794 .halt_reg = 0xb124,
797 .enable_reg = 0xb124,
798 .enable_mask = BIT(0),
807 .halt_reg = 0xb0f0,
810 .enable_reg = 0xb0f0,
811 .enable_mask = BIT(0),
825 .halt_reg = 0xb164,
828 .enable_reg = 0xb164,
829 .enable_mask = BIT(0),
843 .halt_reg = 0xb144,
846 .enable_reg = 0xb144,
847 .enable_mask = BIT(0),
861 .halt_reg = 0xb11c,
864 .enable_reg = 0xb11c,
865 .enable_mask = BIT(0),
879 .halt_reg = 0x501c,
882 .enable_reg = 0x501c,
883 .enable_mask = BIT(0),
897 .halt_reg = 0x5040,
900 .enable_reg = 0x5040,
901 .enable_mask = BIT(0),
915 .halt_reg = 0x5064,
918 .enable_reg = 0x5064,
919 .enable_mask = BIT(0),
933 .halt_reg = 0x5088,
936 .enable_reg = 0x5088,
937 .enable_mask = BIT(0),
951 .halt_reg = 0x5020,
954 .enable_reg = 0x5020,
955 .enable_mask = BIT(0),
969 .halt_reg = 0x5044,
972 .enable_reg = 0x5044,
973 .enable_mask = BIT(0),
987 .halt_reg = 0x5068,
990 .enable_reg = 0x5068,
991 .enable_mask = BIT(0),
1005 .halt_reg = 0x508c,
1008 .enable_reg = 0x508c,
1009 .enable_mask = BIT(0),
1023 .halt_reg = 0xb0a0,
1026 .enable_reg = 0xb0a0,
1027 .enable_mask = BIT(0),
1041 .halt_reg = 0x9080,
1044 .enable_reg = 0x9080,
1045 .enable_mask = BIT(0),
1054 .halt_reg = 0x9028,
1057 .enable_reg = 0x9028,
1058 .enable_mask = BIT(0),
1072 .halt_reg = 0x907c,
1075 .enable_reg = 0x907c,
1076 .enable_mask = BIT(0),
1090 .halt_reg = 0x9054,
1093 .enable_reg = 0x9054,
1094 .enable_mask = BIT(0),
1108 .halt_reg = 0x9038,
1111 .enable_reg = 0x9038,
1112 .enable_mask = BIT(0),
1126 .halt_reg = 0xa058,
1129 .enable_reg = 0xa058,
1130 .enable_mask = BIT(0),
1139 .halt_reg = 0xa028,
1142 .enable_reg = 0xa028,
1143 .enable_mask = BIT(0),
1157 .halt_reg = 0xa054,
1160 .enable_reg = 0xa054,
1161 .enable_mask = BIT(0),
1175 .halt_reg = 0xa04c,
1178 .enable_reg = 0xa04c,
1179 .enable_mask = BIT(0),
1193 .halt_reg = 0xa030,
1196 .enable_reg = 0xa030,
1197 .enable_mask = BIT(0),
1211 .halt_reg = 0xb01c,
1214 .enable_reg = 0xb01c,
1215 .enable_mask = BIT(0),
1229 .halt_reg = 0xb044,
1232 .enable_reg = 0xb044,
1233 .enable_mask = BIT(0),
1247 .halt_reg = 0xb03c,
1250 .enable_reg = 0xb03c,
1251 .enable_mask = BIT(0),
1265 .halt_reg = 0x7040,
1268 .enable_reg = 0x7040,
1269 .enable_mask = BIT(0),
1283 .halt_reg = 0x703c,
1286 .enable_reg = 0x703c,
1287 .enable_mask = BIT(0),
1301 .halt_reg = 0x7038,
1304 .enable_reg = 0x7038,
1305 .enable_mask = BIT(0),
1314 .halt_reg = 0x7028,
1317 .enable_reg = 0x7028,
1318 .enable_mask = BIT(0),
1332 .halt_reg = 0xb064,
1335 .enable_reg = 0xb064,
1336 .enable_mask = BIT(0),
1350 .halt_reg = 0xb110,
1353 .enable_reg = 0xb110,
1354 .enable_mask = BIT(0),
1368 .halt_reg = 0x401c,
1371 .enable_reg = 0x401c,
1372 .enable_mask = BIT(0),
1386 .halt_reg = 0x403c,
1389 .enable_reg = 0x403c,
1390 .enable_mask = BIT(0),
1404 .halt_reg = 0x405c,
1407 .enable_reg = 0x405c,
1408 .enable_mask = BIT(0),
1422 .halt_reg = 0x407c,
1425 .enable_reg = 0x407c,
1426 .enable_mask = BIT(0),
1440 .halt_reg = 0x409c,
1443 .enable_reg = 0x409c,
1444 .enable_mask = BIT(0),
1458 .halt_reg = 0xb140,
1461 .enable_reg = 0xb140,
1462 .enable_mask = BIT(0),
1471 .halt_reg = 0xb0a8,
1474 .enable_reg = 0xb0a8,
1475 .enable_mask = BIT(0),
1484 .gdscr = 0xb134,
1492 .gdscr = 0x6004,
1502 .gdscr = 0x9004,
1511 .gdscr = 0xa004,
1520 .gdscr = 0x7004,
1622 .max_register = 0xd028,
1648 if (ret < 0) in cam_cc_sc7180_probe()
1652 if (ret < 0) in cam_cc_sc7180_probe()
1656 if (ret < 0) { in cam_cc_sc7180_probe()
1662 if (ret < 0) { in cam_cc_sc7180_probe()
1685 if (ret < 0) { in cam_cc_sc7180_probe()
1690 return 0; in cam_cc_sc7180_probe()