1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/pxa-clock.h>
17 #include "clk-pxa.h"
23 #define MDREFR_K2FREE	(1 << 25)	/* SDRAM Free-Running Control */
24 #define MDREFR_K1FREE	(1 << 24)	/* SDRAM Free-Running Control */
25 #define MDREFR_K0FREE	(1 << 23)	/* SDRAM Free-Running Control */
26 #define MDREFR_SLFRSH	(1 << 22)	/* SDRAM Self-Refresh Control/Status */
27 #define MDREFR_APD	(1 << 20)	/* SDRAM/SSRAM Auto-Power-Down Enable */
63 	if (!pclk->is_in_low_power || pclk->is_in_low_power())  in cken_recalc_rate()
64 		fix = &pclk->lp;  in cken_recalc_rate()
66 		fix = &pclk->hp;  in cken_recalc_rate()
67 	__clk_hw_set_clk(&fix->hw, hw);  in cken_recalc_rate()
68 	return clk_fixed_factor_ops.recalc_rate(&fix->hw, parent_rate);  in cken_recalc_rate()
79 	if (!pclk->is_in_low_power)  in cken_get_parent()
81 	return pclk->is_in_low_power() ? 0 : 1;  in cken_get_parent()
109 			return -ENOMEM;  in clk_pxa_cken_init()
110 		pxa_clk->is_in_low_power = clks[i].is_in_low_power;  in clk_pxa_cken_init()
111 		pxa_clk->lp = clks[i].lp;  in clk_pxa_cken_init()
112 		pxa_clk->hp = clks[i].hp;  in clk_pxa_cken_init()
113 		pxa_clk->gate = clks[i].gate;  in clk_pxa_cken_init()
114 		pxa_clk->gate.reg = clk_regs + clks[i].cken_reg;  in clk_pxa_cken_init()
115 		pxa_clk->gate.lock = &pxa_clk_lock;  in clk_pxa_cken_init()
118 					     &pxa_clk->hw, &cken_mux_ops,  in clk_pxa_cken_init()
119 					     &pxa_clk->hw, &cken_rate_ops,  in clk_pxa_cken_init()
120 					     &pxa_clk->gate.hw, &clk_gate_ops,  in clk_pxa_cken_init()
147 	"	b	2f\n"  in pxa2xx_core_turbo_switch()
150 	"	b	3f\n"  in pxa2xx_core_turbo_switch()
151 	"2:	b	1b\n"  in pxa2xx_core_turbo_switch()
162 	unsigned int clkcfg = freq->clkcfg;  in pxa2xx_cpll_change()
174 	if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(freq->membus_khz)) {  in pxa2xx_cpll_change()
176 		preset_mdrefr |= mdrefr_dri(freq->membus_khz);  in pxa2xx_cpll_change()
180 		mdrefr_dri(freq->membus_khz);  in pxa2xx_cpll_change()
186 	if (freq->div2) {  in pxa2xx_cpll_change()
194 	writel(freq->cccr, cccr);  in pxa2xx_cpll_change()
198 	"	b	2f\n"  in pxa2xx_cpll_change()
203 	"	b	3f\n"  in pxa2xx_cpll_change()
204 	"2:	b	1b\n"  in pxa2xx_cpll_change()
217 	int i, closest_below = -1, closest_above = -1;  in pxa2xx_determine_rate()
218 	unsigned long rate;  in pxa2xx_determine_rate()  local
221 		rate = freqs[i].cpll;  in pxa2xx_determine_rate()
222 		if (rate == req->rate)  in pxa2xx_determine_rate()
224 		if (rate < req->min_rate)  in pxa2xx_determine_rate()
226 		if (rate > req->max_rate)  in pxa2xx_determine_rate()
228 		if (rate <= req->rate)  in pxa2xx_determine_rate()
230 		if ((rate >= req->rate) && (closest_above == -1))  in pxa2xx_determine_rate()
234 	req->best_parent_hw = NULL;  in pxa2xx_determine_rate()
237 		rate = req->rate;  in pxa2xx_determine_rate()
239 		rate = freqs[closest_below].cpll;  in pxa2xx_determine_rate()
241 		rate = freqs[closest_above].cpll;  in pxa2xx_determine_rate()
243 		pr_debug("%s(rate=%lu) no match\n", __func__, req->rate);  in pxa2xx_determine_rate()
244 		return -EINVAL;  in pxa2xx_determine_rate()
247 	pr_debug("%s(rate=%lu) rate=%lu\n", __func__, req->rate, rate);  in pxa2xx_determine_rate()
248 	req->rate = rate;  in pxa2xx_determine_rate()