1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
65 /* Fractional PLL operating modes */
78 static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg)  in pll_readl()  argument
80 	return readl(pll->base + reg);  in pll_readl()
83 static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg)  in pll_writel()  argument
85 	writel(val, pll->base + reg);  in pll_writel()
88 static inline void pll_lock(struct pistachio_clk_pll *pll)  in pll_lock()  argument
90 	while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))  in pll_lock()
107 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_frac_get_mode()  local
110 	val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD;  in pll_frac_get_mode()
116 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_frac_set_mode()  local
119 	val = pll_readl(pll, PLL_CTRL3);  in pll_frac_set_mode()
125 	pll_writel(pll, val, PLL_CTRL3);  in pll_frac_set_mode()
129 pll_get_params(struct pistachio_clk_pll *pll, unsigned long fref,  in pll_get_params()  argument
134 	for (i = 0; i < pll->nr_rates; i++) {  in pll_get_params()
135 		if (pll->rates[i].fref == fref && pll->rates[i].fout == fout)  in pll_get_params()
136 			return &pll->rates[i];  in pll_get_params()
144 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_determine_rate()  local
147 	for (i = 0; i < pll->nr_rates; i++) {  in pll_determine_rate()
148 		if (i > 0 && pll->rates[i].fref == req->best_parent_rate &&  in pll_determine_rate()
149 		    pll->rates[i].fout <= req->rate) {  in pll_determine_rate()
150 			req->rate = pll->rates[i - 1].fout;  in pll_determine_rate()
156 	req->rate = pll->rates[0].fout;  in pll_determine_rate()
163 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_enable()  local
166 	val = pll_readl(pll, PLL_CTRL3);  in pll_gf40lp_frac_enable()
169 	pll_writel(pll, val, PLL_CTRL3);  in pll_gf40lp_frac_enable()
171 	val = pll_readl(pll, PLL_CTRL4);  in pll_gf40lp_frac_enable()
173 	pll_writel(pll, val, PLL_CTRL4);  in pll_gf40lp_frac_enable()
175 	pll_lock(pll);  in pll_gf40lp_frac_enable()
182 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_disable()  local
185 	val = pll_readl(pll, PLL_CTRL3);  in pll_gf40lp_frac_disable()
187 	pll_writel(pll, val, PLL_CTRL3);  in pll_gf40lp_frac_disable()
192 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_is_enabled()  local
194 	return !(pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_PD);  in pll_gf40lp_frac_is_enabled()
200 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_set_rate()  local
207 		return -EINVAL;  in pll_gf40lp_frac_set_rate()
209 	params = pll_get_params(pll, parent_rate, rate);  in pll_gf40lp_frac_set_rate()
210 	if (!params || !params->refdiv)  in pll_gf40lp_frac_set_rate()
211 		return -EINVAL;  in pll_gf40lp_frac_set_rate()
214 	vco = params->fref;  in pll_gf40lp_frac_set_rate()
215 	vco *= (params->fbdiv << 24) + params->frac;  in pll_gf40lp_frac_set_rate()
216 	vco = div64_u64(vco, params->refdiv << 24);  in pll_gf40lp_frac_set_rate()
219 		pr_warn("%s: VCO %llu is out of range %lu..%lu\n", name, vco,  in pll_gf40lp_frac_set_rate()
222 	val = div64_u64(params->fref, params->refdiv);  in pll_gf40lp_frac_set_rate()
230 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_frac_set_rate()
233 	val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) |  in pll_gf40lp_frac_set_rate()
234 		(params->fbdiv << PLL_CTRL1_FBDIV_SHIFT);  in pll_gf40lp_frac_set_rate()
235 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_frac_set_rate()
237 	val = pll_readl(pll, PLL_CTRL2);  in pll_gf40lp_frac_set_rate()
244 	    (params->postdiv1 != old_postdiv1 ||  in pll_gf40lp_frac_set_rate()
245 	     params->postdiv2 != old_postdiv2))  in pll_gf40lp_frac_set_rate()
246 		pr_warn("%s: changing postdiv while PLL is enabled\n", name);  in pll_gf40lp_frac_set_rate()
248 	if (params->postdiv2 > params->postdiv1)  in pll_gf40lp_frac_set_rate()
256 	val |= (params->frac << PLL_FRAC_CTRL2_FRAC_SHIFT) |  in pll_gf40lp_frac_set_rate()
257 		(params->postdiv1 << PLL_FRAC_CTRL2_POSTDIV1_SHIFT) |  in pll_gf40lp_frac_set_rate()
258 		(params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT);  in pll_gf40lp_frac_set_rate()
259 	pll_writel(pll, val, PLL_CTRL2);  in pll_gf40lp_frac_set_rate()
262 	if (params->frac)  in pll_gf40lp_frac_set_rate()
268 		pll_lock(pll);  in pll_gf40lp_frac_set_rate()
276 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_recalc_rate()  local
279 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_frac_recalc_rate()
283 	val = pll_readl(pll, PLL_CTRL2);  in pll_gf40lp_frac_recalc_rate()
320 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_enable()  local
323 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_enable()
326 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_laint_enable()
328 	val = pll_readl(pll, PLL_CTRL2);  in pll_gf40lp_laint_enable()
330 	pll_writel(pll, val, PLL_CTRL2);  in pll_gf40lp_laint_enable()
332 	pll_lock(pll);  in pll_gf40lp_laint_enable()
339 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_disable()  local
342 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_disable()
344 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_laint_disable()
349 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_is_enabled()  local
351 	return !(pll_readl(pll, PLL_CTRL1) & PLL_INT_CTRL1_PD);  in pll_gf40lp_laint_is_enabled()
357 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_set_rate()  local
364 		return -EINVAL;  in pll_gf40lp_laint_set_rate()
366 	params = pll_get_params(pll, parent_rate, rate);  in pll_gf40lp_laint_set_rate()
367 	if (!params || !params->refdiv)  in pll_gf40lp_laint_set_rate()
368 		return -EINVAL;  in pll_gf40lp_laint_set_rate()
370 	vco = div_u64(params->fref * params->fbdiv, params->refdiv);  in pll_gf40lp_laint_set_rate()
372 		pr_warn("%s: VCO %u is out of range %lu..%lu\n", name, vco,  in pll_gf40lp_laint_set_rate()
375 	val = div_u64(params->fref, params->refdiv);  in pll_gf40lp_laint_set_rate()
383 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_set_rate()
390 	    (params->postdiv1 != old_postdiv1 ||  in pll_gf40lp_laint_set_rate()
391 	     params->postdiv2 != old_postdiv2))  in pll_gf40lp_laint_set_rate()
392 		pr_warn("%s: changing postdiv while PLL is enabled\n", name);  in pll_gf40lp_laint_set_rate()
394 	if (params->postdiv2 > params->postdiv1)  in pll_gf40lp_laint_set_rate()
401 	val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) |  in pll_gf40lp_laint_set_rate()
402 		(params->fbdiv << PLL_CTRL1_FBDIV_SHIFT) |  in pll_gf40lp_laint_set_rate()
403 		(params->postdiv1 << PLL_INT_CTRL1_POSTDIV1_SHIFT) |  in pll_gf40lp_laint_set_rate()
404 		(params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT);  in pll_gf40lp_laint_set_rate()
405 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_laint_set_rate()
408 		pll_lock(pll);  in pll_gf40lp_laint_set_rate()
416 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_recalc_rate()  local
420 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_recalc_rate()
456 	struct pistachio_clk_pll *pll;  in pll_register()  local
460 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in pll_register()
461 	if (!pll)  in pll_register()
462 		return ERR_PTR(-ENOMEM);  in pll_register()
483 		pr_err("Unrecognized PLL type %u\n", type);  in pll_register()
484 		kfree(pll);  in pll_register()
485 		return ERR_PTR(-EINVAL);  in pll_register()
488 	pll->hw.init = &init;  in pll_register()
489 	pll->base = base;  in pll_register()
490 	pll->rates = rates;  in pll_register()
491 	pll->nr_rates = nr_rates;  in pll_register()
493 	clk = clk_register(NULL, &pll->hw);  in pll_register()
495 		kfree(pll);  in pll_register()
501 				struct pistachio_pll *pll,  in pistachio_clk_register_pll()  argument
508 		clk = pll_register(pll[i].name, pll[i].parent,  in pistachio_clk_register_pll()
509 				   0, p->base + pll[i].reg_base,  in pistachio_clk_register_pll()
510 				   pll[i].type, pll[i].rates,  in pistachio_clk_register_pll()
511 				   pll[i].nr_rates);  in pistachio_clk_register_pll()
512 		p->clk_data.clks[pll[i].id] = clk;  in pistachio_clk_register_pll()