1 // SPDX-License-Identifier: GPL-2.0-only
4  * Author: Chi-Fang Li <cfli0@nuvoton.com>
7 #include <linux/clk-provider.h>
8 #include <linux/device.h>
12 #include "clk-ma35d1.h"
18 	u8 width;  member
35 	val = readl_relaxed(dclk->reg) >> dclk->shift;  in ma35d1_clkdiv_recalc_rate()
36 	val &= clk_div_mask(dclk->width);  in ma35d1_clkdiv_recalc_rate()
38 	return divider_recalc_rate(hw, parent_rate, val, dclk->table,  in ma35d1_clkdiv_recalc_rate()
39 				   CLK_DIVIDER_ROUND_CLOSEST, dclk->width);  in ma35d1_clkdiv_recalc_rate()
47 	req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,  in ma35d1_clkdiv_determine_rate()
48 				       dclk->table, dclk->width,  in ma35d1_clkdiv_determine_rate()
61 	value = divider_get_val(rate, parent_rate, dclk->table,  in ma35d1_clkdiv_set_rate()
62 				dclk->width, CLK_DIVIDER_ROUND_CLOSEST);  in ma35d1_clkdiv_set_rate()
64 	spin_lock_irqsave(dclk->lock, flags);  in ma35d1_clkdiv_set_rate()
66 	data = readl_relaxed(dclk->reg);  in ma35d1_clkdiv_set_rate()
67 	data &= ~(clk_div_mask(dclk->width) << dclk->shift);  in ma35d1_clkdiv_set_rate()
68 	data |= (value - 1) << dclk->shift;  in ma35d1_clkdiv_set_rate()
69 	data |= dclk->mask;  in ma35d1_clkdiv_set_rate()
70 	writel_relaxed(data, dclk->reg);  in ma35d1_clkdiv_set_rate()
72 	spin_unlock_irqrestore(dclk->lock, flags);  in ma35d1_clkdiv_set_rate()
82 struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name,  in ma35d1_reg_adc_clkdiv()
85 				     u8 shift, u8 width, u32 mask_bit)  in ma35d1_reg_adc_clkdiv()  argument
98 		return ERR_PTR(-ENOMEM);  in ma35d1_reg_adc_clkdiv()
100 	max_div = clk_div_mask(width) + 1;  in ma35d1_reg_adc_clkdiv()
105 		return ERR_PTR(-ENOMEM);  in ma35d1_reg_adc_clkdiv()
122 	div->reg = reg;  in ma35d1_reg_adc_clkdiv()
123 	div->shift = shift;  in ma35d1_reg_adc_clkdiv()
124 	div->width = width;  in ma35d1_reg_adc_clkdiv()
125 	div->mask = mask_bit ? BIT(mask_bit) : 0;  in ma35d1_reg_adc_clkdiv()
126 	div->lock = lock;  in ma35d1_reg_adc_clkdiv()
127 	div->hw.init = &init;  in ma35d1_reg_adc_clkdiv()
128 	div->table = table;  in ma35d1_reg_adc_clkdiv()
130 	hw = &div->hw;  in ma35d1_reg_adc_clkdiv()