Lines Matching +full:power +full:- +full:gate

1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
14  * struct clk_pll - mxs pll clock
17  * @power: the shift of power bit
20  * The mxs pll is a fixed rate clock with power and gate control,
21  * and the shift of gate bit is always 31.
26 	u8 power;  member
36 	writel_relaxed(1 << pll->power, pll->base + SET);  in clk_pll_prepare()
47 	writel_relaxed(1 << pll->power, pll->base + CLR);  in clk_pll_unprepare()
54 	writel_relaxed(1 << 31, pll->base + CLR);  in clk_pll_enable()
63 	writel_relaxed(1 << 31, pll->base + SET);  in clk_pll_disable()
71 	return pll->rate;  in clk_pll_recalc_rate()
83 			void __iomem *base, u8 power, unsigned long rate)  in mxs_clk_pll()  argument
91 		return ERR_PTR(-ENOMEM);  in mxs_clk_pll()
99 	pll->base = base;  in mxs_clk_pll()
100 	pll->rate = rate;  in mxs_clk_pll()
101 	pll->power = power;  in mxs_clk_pll()
102 	pll->hw.init = &init;  in mxs_clk_pll()
104 	clk = clk_register(NULL, &pll->hw);  in mxs_clk_pll()