14  * struct clk_pll - mxs pll clock
15  * @hw: clk_hw for the pll
16  * @base: base address of the pll
18  * @rate: the clock rate of the pll
20  * The mxs pll is a fixed rate clock with power and gate control,
34 	struct clk_pll *pll = to_clk_pll(hw);  in clk_pll_prepare()  local
36 	writel_relaxed(1 << pll->power, pll->base + SET);  in clk_pll_prepare()
45 	struct clk_pll *pll = to_clk_pll(hw);  in clk_pll_unprepare()  local
47 	writel_relaxed(1 << pll->power, pll->base + CLR);  in clk_pll_unprepare()
52 	struct clk_pll *pll = to_clk_pll(hw);  in clk_pll_enable()  local
54 	writel_relaxed(1 << 31, pll->base + CLR);  in clk_pll_enable()
61 	struct clk_pll *pll = to_clk_pll(hw);  in clk_pll_disable()  local
63 	writel_relaxed(1 << 31, pll->base + SET);  in clk_pll_disable()
69 	struct clk_pll *pll = to_clk_pll(hw);  in clk_pll_recalc_rate()  local
71 	return pll->rate;  in clk_pll_recalc_rate()
85 	struct clk_pll *pll;  in mxs_clk_pll()  local
89 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in mxs_clk_pll()
90 	if (!pll)  in mxs_clk_pll()
99 	pll->base = base;  in mxs_clk_pll()
100 	pll->rate = rate;  in mxs_clk_pll()
101 	pll->power = power;  in mxs_clk_pll()
102 	pll->hw.init = &init;  in mxs_clk_pll()
104 	clk = clk_register(NULL, &pll->hw);  in mxs_clk_pll()
106 		kfree(pll);  in mxs_clk_pll()