1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
8 #include <linux/io.h>
13  * struct clk_frac - mxs fractional divider clock
15  * @reg: register address
17  * @width: the divider bit width
25 	void __iomem *reg;  member
27 	u8 width;  member
40 	div = readl_relaxed(frac->reg) >> frac->shift;  in clk_frac_recalc_rate()
41 	div &= (1 << frac->width) - 1;  in clk_frac_recalc_rate()
44 	return tmp_rate >> frac->width;  in clk_frac_recalc_rate()
51 	unsigned long parent_rate = req->best_parent_rate;  in clk_frac_determine_rate()
55 	if (req->rate > parent_rate)  in clk_frac_determine_rate()
56 		return -EINVAL;  in clk_frac_determine_rate()
58 	tmp = req->rate;  in clk_frac_determine_rate()
59 	tmp <<= frac->width;  in clk_frac_determine_rate()
64 		return -EINVAL;  in clk_frac_determine_rate()
67 	result = tmp_rate >> frac->width;  in clk_frac_determine_rate()
68 	if ((result << frac->width) < tmp_rate)  in clk_frac_determine_rate()
70 	req->rate = result;  in clk_frac_determine_rate()
84 		return -EINVAL;  in clk_frac_set_rate()
87 	tmp <<= frac->width;  in clk_frac_set_rate()
92 		return -EINVAL;  in clk_frac_set_rate()
96 	val = readl_relaxed(frac->reg);  in clk_frac_set_rate()
97 	val &= ~(((1 << frac->width) - 1) << frac->shift);  in clk_frac_set_rate()
98 	val |= div << frac->shift;  in clk_frac_set_rate()
99 	writel_relaxed(val, frac->reg);  in clk_frac_set_rate()
103 	return mxs_clk_wait(frac->reg, frac->busy);  in clk_frac_set_rate()
113 			 void __iomem *reg, u8 shift, u8 width, u8 busy)  in mxs_clk_frac()  argument
121 		return ERR_PTR(-ENOMEM);  in mxs_clk_frac()
129 	frac->reg = reg;  in mxs_clk_frac()
130 	frac->shift = shift;  in mxs_clk_frac()
131 	frac->width = width;  in mxs_clk_frac()
132 	frac->busy = busy;  in mxs_clk_frac()
133 	frac->hw.init = &init;  in mxs_clk_frac()
135 	clk = clk_register(NULL, &frac->hw);  in mxs_clk_frac()