Lines Matching +full:dclk +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 #include <linux/clk-provider.h>
21 * SARL[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
88 { .id = A390_CPU_TO_DCLK, .name = "dclk" },
92 void __iomem *sar, int id, int *mult, int *div) in armada_39x_get_clk_ratio() argument
97 *div = 2; in armada_39x_get_clk_ratio()
101 *div = 4; in armada_39x_get_clk_ratio()
105 *div = 2; in armada_39x_get_clk_ratio()
131 CLK_OF_DECLARE(armada_39x_core_clk, "marvell,armada-390-core-clock",
155 CLK_OF_DECLARE(armada_39x_clk_gating, "marvell,armada-390-gating-clock",