1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/microchip,mpfs-clock.h>
12 #include <soc/microchip/mpfs.h>
84  * mpfs clk block while a software locked register is being written.
104  * 100 and 125 MHz, as the rtc reference is required to be 1 MHz.
120 	void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;  in mpfs_clk_msspll_recalc_rate()
121 	void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;  in mpfs_clk_msspll_recalc_rate()
159 		msspll_hw->base = data->msspll_base;  in mpfs_clk_register_mssplls()
160 		ret = devm_clk_hw_register(dev, &msspll_hw->hw);  in mpfs_clk_register_mssplls()
165 		data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw;  in mpfs_clk_register_mssplls()
207 		msspll_out_hw->output.reg = data->msspll_base + msspll_out_hw->reg_offset;  in mpfs_clk_register_msspll_outs()
208 		ret = devm_clk_hw_register(dev, &msspll_out_hw->output.hw);  in mpfs_clk_register_msspll_outs()
211 					     msspll_out_hw->id);  in mpfs_clk_register_msspll_outs()
213 		data->hw_data.hws[msspll_out_hw->id] = &msspll_out_hw->output.hw;  in mpfs_clk_register_msspll_outs()
267 		cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset;  in mpfs_clk_register_cfgs()
268 		ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw);  in mpfs_clk_register_cfgs()
271 					     cfg_hw->id);  in mpfs_clk_register_cfgs()
273 		id = cfg_hw->id;  in mpfs_clk_register_cfgs()
274 		data->hw_data.hws[id] = &cfg_hw->cfg.hw;  in mpfs_clk_register_cfgs()
281  * peripheral clocks - devices connected to axi or ahb buses.
296  * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt
298  * - CLK_MMUART0: reserved by the hss
299  * - CLK_DDRC: provides clock to the ddr subsystem
300  * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop
302  * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect)
305  * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire.
349 		periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR;  in mpfs_clk_register_periphs()
350 		ret = devm_clk_hw_register(dev, &periph_hw->periph.hw);  in mpfs_clk_register_periphs()
353 					     periph_hw->id);  in mpfs_clk_register_periphs()
356 		data->hw_data.hws[id] = &periph_hw->periph.hw;  in mpfs_clk_register_periphs()
364 	struct device *dev = &pdev->dev;  in mpfs_clk_probe()
375 		return -ENOMEM;  in mpfs_clk_probe()
377 	clk_data->base = devm_platform_ioremap_resource(pdev, 0);  in mpfs_clk_probe()
378 	if (IS_ERR(clk_data->base))  in mpfs_clk_probe()
379 		return PTR_ERR(clk_data->base);  in mpfs_clk_probe()
381 	clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1);  in mpfs_clk_probe()
382 	if (IS_ERR(clk_data->msspll_base))  in mpfs_clk_probe()
383 		return PTR_ERR(clk_data->msspll_base);  in mpfs_clk_probe()
385 	clk_data->hw_data.num = num_clks;  in mpfs_clk_probe()
386 	clk_data->dev = dev;  in mpfs_clk_probe()
409 	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);  in mpfs_clk_probe()
413 	return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RESET_CR);  in mpfs_clk_probe()
417 	{ .compatible = "microchip,mpfs-clkcfg", },
425 		.name = "microchip-mpfs-clkcfg",