965 	struct pic32_sec_osc *sosc = clkhw_to_sosc(hw);  in sosc_clk_enable()  local
970 	writel(sosc->enable_mask, PIC32_SET(sosc->enable_reg));  in sosc_clk_enable()
973 	return readl_poll_timeout_atomic(sosc->status_reg, v,  in sosc_clk_enable()
974 					 v & sosc->status_mask, 1, 100);  in sosc_clk_enable()
979 	struct pic32_sec_osc *sosc = clkhw_to_sosc(hw);  in sosc_clk_disable()  local
982 	writel(sosc->enable_mask, PIC32_CLR(sosc->enable_reg));  in sosc_clk_disable()
987 	struct pic32_sec_osc *sosc = clkhw_to_sosc(hw);  in sosc_clk_is_enabled()  local
991 	enabled = readl(sosc->enable_reg) & sosc->enable_mask;  in sosc_clk_is_enabled()
992 	ready = readl(sosc->status_reg) & sosc->status_mask;  in sosc_clk_is_enabled()
1013 	struct pic32_sec_osc *sosc;  in pic32_sosc_clk_register()  local
1015 	sosc = devm_kzalloc(core->dev, sizeof(*sosc), GFP_KERNEL);  in pic32_sosc_clk_register()
1016 	if (!sosc)  in pic32_sosc_clk_register()
1019 	sosc->core = core;  in pic32_sosc_clk_register()
1020 	sosc->hw.init = &data->init_data;  in pic32_sosc_clk_register()
1021 	sosc->fixed_rate = data->fixed_rate;  in pic32_sosc_clk_register()
1022 	sosc->enable_mask = data->enable_mask;  in pic32_sosc_clk_register()
1023 	sosc->status_mask = data->status_mask;  in pic32_sosc_clk_register()
1024 	sosc->enable_reg = data->enable_reg + core->iobase;  in pic32_sosc_clk_register()
1025 	sosc->status_reg = data->status_reg + core->iobase;  in pic32_sosc_clk_register()
1027 	return devm_clk_register(core->dev, &sosc->hw);  in pic32_sosc_clk_register()