Lines Matching +full:duty +full:- +full:cycle
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
12 * The duty cycle may also be set for the LR clock variant. The duty cycle
15 * hi = [0 - val]
19 #include <linux/clk-provider.h>
22 #include "clk-regmap.h"
23 #include "sclk-div.h"
28 return (struct meson_sclk_div_data *)clk->data;
33 return (1 << sclk->div.width) - 1;
84 if (abs(rate - now) < abs(rate - best)) {
106 div = sclk_div_bestdiv(hw, req->rate, &req->best_parent_rate, sclk);
107 req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
115 unsigned int hi = DIV_ROUND_CLOSEST(sclk->cached_div *
116 sclk->cached_duty.num,
117 sclk->cached_duty.den);
120 hi -= 1;
122 meson_parm_write(clk->map, &sclk->hi, hi);
126 struct clk_duty *duty)
131 if (MESON_PARM_APPLICABLE(&sclk->hi)) {
132 memcpy(&sclk->cached_duty, duty, sizeof(*duty));
140 struct clk_duty *duty)
146 if (!MESON_PARM_APPLICABLE(&sclk->hi)) {
147 duty->num = 1;
148 duty->den = 2;
152 hi = meson_parm_read(clk->map, &sclk->hi);
153 duty->num = hi + 1;
154 duty->den = sclk->cached_div;
161 if (MESON_PARM_APPLICABLE(&sclk->hi))
164 meson_parm_write(clk->map, &sclk->div, sclk->cached_div - 1);
174 sclk->cached_div = sclk_div_getdiv(hw, rate, prate, maxdiv);
188 return DIV_ROUND_UP_ULL((u64)prate, sclk->cached_div);
206 meson_parm_write(clk->map, &sclk->div, 0);
214 if (meson_parm_read(clk->map, &sclk->div))
231 val = meson_parm_read(clk->map, &sclk->div);
235 sclk->cached_div = sclk_div_maxdiv(sclk);
237 sclk->cached_div = val + 1;
239 sclk_div_get_duty_cycle(hw, &sclk->cached_duty);