Lines Matching +full:data +full:- +full:width
1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
5 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
9 #include <linux/clk-provider.h>
13 #include "clk-mpll.h"
14 #include "clk-pll.h"
15 #include "clk-regmap.h"
16 #include "s4-pll.h"
17 #include "meson-clkc-utils.h"
18 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
23 * in the kernel phase. Write of fixed PLL-related register will cause the system to crash.
28 .data = &(struct meson_clk_pll_data){
32 .width = 1,
37 .width = 8,
42 .width = 17,
47 .width = 5,
52 .width = 1,
57 .width = 1,
71 .data = &(struct clk_regmap_div_data){
74 .width = 2,
103 .data = &(struct clk_regmap_gate_data){
129 .data = &(struct clk_regmap_gate_data){
155 .data = &(struct clk_regmap_gate_data){
181 .data = &(struct clk_regmap_gate_data){
207 .data = &(struct clk_regmap_gate_data){
235 .data = &(struct clk_regmap_gate_data){
267 .data = &(struct meson_clk_pll_data){
271 .width = 1,
276 .width = 8,
281 .width = 5,
286 .width = 1,
291 .width = 1,
308 .data = &(struct clk_regmap_div_data){
311 .width = 3,
338 .data = &(struct meson_clk_pll_data){
342 .width = 1,
347 .width = 8,
352 .width = 5,
357 .width = 17,
362 .width = 1,
367 .width = 1,
386 .data = &(struct clk_regmap_div_data){
389 .width = 2,
405 .data = &(struct meson_clk_pll_data){
409 .width = 1,
414 .width = 8,
419 .width = 5,
424 .width = 1,
429 .width = 1,
444 .data = &(struct clk_regmap_div_data){
447 .width = 4,
462 .data = &(struct clk_regmap_div_data){
465 .width = 2,
493 .data = &(struct clk_regmap_mux_data){
527 .data = &(struct meson_clk_mpll_data){
531 .width = 14,
536 .width = 1,
541 .width = 9,
546 .width = 1,
562 .data = &(struct clk_regmap_gate_data){
580 .data = &(struct meson_clk_mpll_data){
584 .width = 14,
589 .width = 1,
594 .width = 9,
599 .width = 1,
615 .data = &(struct clk_regmap_gate_data){
633 .data = &(struct meson_clk_mpll_data){
637 .width = 14,
642 .width = 1,
647 .width = 9,
652 .width = 1,
668 .data = &(struct clk_regmap_gate_data){
686 .data = &(struct meson_clk_mpll_data){
690 .width = 14,
695 .width = 1,
700 .width = 9,
705 .width = 1,
721 .data = &(struct clk_regmap_gate_data){
815 struct device *dev = &pdev->dev; in meson_s4_pll_probe()
837 s4_pll_clk_regmaps[i]->map = regmap; in meson_s4_pll_probe()
857 .compatible = "amlogic,s4-pll-clkc",
866 .name = "s4-pll-clkc",