Lines Matching +full:data +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
14 #include "clk-regmap.h"
15 #include "clk-pll.h"
16 #include "clk-mpll.h"
17 #include "meson-eeclk.h"
18 #include "vid-pll-div.h"
20 #include <dt-bindings/clock/gxbb-clkc.h>
87 .data = &(struct meson_clk_pll_data){
91 .width = 1,
96 .width = 9,
101 .width = 5,
106 .width = 12,
111 .width = 1,
116 .width = 1,
130 .data = &(struct clk_regmap_div_data){
133 .width = 2,
164 .data = &(struct meson_clk_pll_data){
168 .width = 1,
173 .width = 9,
178 .width = 5,
183 .width = 12,
188 .width = 1,
193 .width = 1,
212 .data = &(struct meson_clk_pll_data){
216 .width = 1,
221 .width = 9,
226 .width = 5,
237 .width = 10,
242 .width = 1,
247 .width = 1,
266 .data = &(struct clk_regmap_div_data){
269 .width = 2,
284 .data = &(struct clk_regmap_div_data){
287 .width = 2,
302 .data = &(struct clk_regmap_div_data){
305 .width = 2,
320 .data = &(struct clk_regmap_div_data){
323 .width = 2,
338 .data = &(struct clk_regmap_div_data){
341 .width = 2,
356 .data = &(struct clk_regmap_div_data){
359 .width = 2,
374 .data = &(struct meson_clk_pll_data){
378 .width = 1,
383 .width = 9,
388 .width = 5,
393 .width = 1,
398 .width = 1,
412 .data = &(struct clk_regmap_div_data){
415 .width = 2,
436 .data = &(struct meson_clk_pll_data){
440 .width = 1,
445 .width = 9,
450 .width = 5,
455 .width = 1,
460 .width = 1,
485 .data = &(struct meson_clk_pll_data){
489 .width = 1,
494 .width = 9,
499 .width = 5,
504 .width = 10,
509 .width = 1,
514 .width = 1,
531 .data = &(struct clk_regmap_div_data){
534 .width = 2,
549 .index = -1,
570 .data = &(struct clk_regmap_gate_data){
597 .data = &(struct clk_regmap_gate_data){
616 * b) CCF has a clock hand-off mechanism to make the sure the
635 .data = &(struct clk_regmap_gate_data){
661 .data = &(struct clk_regmap_gate_data){
687 .data = &(struct clk_regmap_gate_data){
702 .data = &(struct clk_regmap_div_data){
705 .width = 1,
716 .data = &(struct meson_clk_mpll_data){
720 .width = 14,
725 .width = 1,
730 .width = 9,
744 .data = &(struct meson_clk_mpll_data){
748 .width = 14,
753 .width = 1,
758 .width = 9,
772 .data = &(struct clk_regmap_gate_data){
787 .index = -1,
795 .data = &(struct meson_clk_mpll_data){
799 .width = 14,
804 .width = 1,
809 .width = 9,
823 .data = &(struct clk_regmap_gate_data){
837 .data = &(struct meson_clk_mpll_data){
841 .width = 14,
846 .width = 1,
851 .width = 9,
865 .data = &(struct clk_regmap_gate_data){
890 .data = &(struct clk_regmap_mux_data){
910 .data = &(struct clk_regmap_div_data){
913 .width = 7,
927 .data = &(struct clk_regmap_gate_data){
943 .data = &(struct clk_regmap_mux_data){
961 .data = &(struct clk_regmap_div_data){
964 .width = 8,
978 .data = &(struct clk_regmap_gate_data){
995 * muxed by a glitch-free switch. The CCF can manage this glitch-free
996 * mux because it does top-to-bottom updates the each clock tree and
1012 .data = &(struct clk_regmap_mux_data){
1033 .data = &(struct clk_regmap_div_data){
1036 .width = 7,
1050 .data = &(struct clk_regmap_gate_data){
1066 .data = &(struct clk_regmap_mux_data){
1087 .data = &(struct clk_regmap_div_data){
1090 .width = 7,
1104 .data = &(struct clk_regmap_gate_data){
1125 .data = &(struct clk_regmap_mux_data){
1140 .data = &(struct clk_regmap_mux_data){
1160 .data = &(struct clk_regmap_div_data) {
1163 .width = 8,
1178 .data = &(struct clk_regmap_gate_data){
1194 .data = &(struct clk_regmap_mux_data){
1214 .data = &(struct clk_regmap_div_data){
1217 .width = 8,
1232 .data = &(struct clk_regmap_gate_data){
1248 .data = &(struct clk_regmap_mux_data){
1262 *The parent is specific to origin of the audio data. Let the
1276 { .name = "cts_slow_oscin", .index = -1 },
1282 .data = &(struct clk_regmap_mux_data){
1297 .data = &(struct clk_regmap_div_data){
1300 .width = 14,
1314 .data = &(struct clk_regmap_gate_data){
1345 .data = &(struct clk_regmap_mux_data){
1360 .data = &(struct clk_regmap_div_data){
1363 .width = 7,
1378 .data = &(struct clk_regmap_gate_data){
1395 .data = &(struct clk_regmap_mux_data){
1410 .data = &(struct clk_regmap_div_data){
1413 .width = 7,
1428 .data = &(struct clk_regmap_gate_data){
1445 .data = &(struct clk_regmap_mux_data){
1460 .data = &(struct clk_regmap_div_data){
1463 .width = 7,
1478 .data = &(struct clk_regmap_gate_data){
1503 .data = &(struct clk_regmap_mux_data){
1522 .data = &(struct clk_regmap_div_data){
1525 .width = 7,
1537 .data = &(struct clk_regmap_gate_data){
1551 .data = &(struct clk_regmap_mux_data){
1570 .data = &(struct clk_regmap_div_data){
1573 .width = 7,
1585 .data = &(struct clk_regmap_gate_data){
1599 .data = &(struct clk_regmap_mux_data){
1630 .data = &(struct clk_regmap_mux_data){
1649 .data = &(struct clk_regmap_div_data){
1652 .width = 7,
1666 .data = &(struct clk_regmap_gate_data){
1682 .data = &(struct clk_regmap_mux_data){
1701 .data = &(struct clk_regmap_div_data){
1704 .width = 7,
1718 .data = &(struct clk_regmap_gate_data){
1734 .data = &(struct clk_regmap_mux_data){
1756 .data = &(struct clk_regmap_gate_data){
1772 .data = &(struct meson_vid_pll_div_data){
1776 .width = 15,
1781 .width = 2,
1796 .index = -1,
1812 { .name = "hdmi_pll", .index = -1 },
1816 .data = &(struct clk_regmap_mux_data){
1835 .data = &(struct clk_regmap_gate_data){
1861 .data = &(struct clk_regmap_mux_data){
1881 .data = &(struct clk_regmap_mux_data){
1901 .data = &(struct clk_regmap_gate_data){
1915 .data = &(struct clk_regmap_gate_data){
1929 .data = &(struct clk_regmap_div_data){
1932 .width = 8,
1946 .data = &(struct clk_regmap_div_data){
1949 .width = 8,
1963 .data = &(struct clk_regmap_gate_data){
1977 .data = &(struct clk_regmap_gate_data){
1991 .data = &(struct clk_regmap_gate_data){
2005 .data = &(struct clk_regmap_gate_data){
2019 .data = &(struct clk_regmap_gate_data){
2033 .data = &(struct clk_regmap_gate_data){
2047 .data = &(struct clk_regmap_gate_data){
2061 .data = &(struct clk_regmap_gate_data){
2075 .data = &(struct clk_regmap_gate_data){
2089 .data = &(struct clk_regmap_gate_data){
2103 .data = &(struct clk_regmap_gate_data){
2117 .data = &(struct clk_regmap_gate_data){
2249 .data = &(struct clk_regmap_mux_data){
2265 .data = &(struct clk_regmap_mux_data){
2281 .data = &(struct clk_regmap_mux_data){
2312 .data = &(struct clk_regmap_mux_data){
2334 .data = &(struct clk_regmap_gate_data){
2350 .data = &(struct clk_regmap_gate_data){
2366 .data = &(struct clk_regmap_gate_data){
2382 .data = &(struct clk_regmap_gate_data){
2407 .data = &(struct clk_regmap_mux_data){
2423 .data = &(struct clk_regmap_div_data){
2426 .width = 7,
2438 .data = &(struct clk_regmap_gate_data){
2461 .data = &(struct clk_regmap_mux_data){
2477 .data = &(struct clk_regmap_div_data){
2480 .width = 7,
2495 .data = &(struct clk_regmap_gate_data){
2511 .data = &(struct clk_regmap_mux_data){
2527 .data = &(struct clk_regmap_div_data){
2530 .width = 7,
2545 .data = &(struct clk_regmap_gate_data){
2577 .data = &(struct clk_regmap_mux_data){
2598 .data = &(struct clk_regmap_div_data){
2601 .width = 11,
2615 .data = &(struct clk_regmap_gate_data){
3551 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3552 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3560 .name = "gxbb-clkc",