Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
14 #include "clk-regmap.h"
15 #include "clk-pll.h"
16 #include "clk-mpll.h"
17 #include "meson-eeclk.h"
18 #include "vid-pll-div.h"
20 #include <dt-bindings/clock/gxbb-clkc.h>
87 .data = &(struct meson_clk_pll_data){
90 .shift = 30,
95 .shift = 0,
100 .shift = 9,
105 .shift = 0,
110 .shift = 31,
115 .shift = 29,
130 .data = &(struct clk_regmap_div_data){
132 .shift = 16,
164 .data = &(struct meson_clk_pll_data){
167 .shift = 30,
172 .shift = 0,
177 .shift = 9,
182 .shift = 0,
187 .shift = 31,
192 .shift = 28,
212 .data = &(struct meson_clk_pll_data){
215 .shift = 30,
220 .shift = 0,
225 .shift = 9,
229 * On gxl, there is a register shift due to
236 .shift = 0,
241 .shift = 31,
246 .shift = 28,
266 .data = &(struct clk_regmap_div_data){
268 .shift = 16,
284 .data = &(struct clk_regmap_div_data){
286 .shift = 22,
302 .data = &(struct clk_regmap_div_data){
304 .shift = 18,
320 .data = &(struct clk_regmap_div_data){
322 .shift = 21,
338 .data = &(struct clk_regmap_div_data){
340 .shift = 23,
356 .data = &(struct clk_regmap_div_data){
358 .shift = 19,
374 .data = &(struct meson_clk_pll_data){
377 .shift = 30,
382 .shift = 0,
387 .shift = 9,
392 .shift = 31,
397 .shift = 29,
412 .data = &(struct clk_regmap_div_data){
414 .shift = 10,
436 .data = &(struct meson_clk_pll_data){
439 .shift = 30,
444 .shift = 0,
449 .shift = 9,
454 .shift = 31,
459 .shift = 29,
485 .data = &(struct meson_clk_pll_data){
488 .shift = 30,
493 .shift = 0,
498 .shift = 9,
503 .shift = 0,
508 .shift = 31,
513 .shift = 29,
531 .data = &(struct clk_regmap_div_data){
533 .shift = 16,
549 .index = -1,
570 .data = &(struct clk_regmap_gate_data){
597 .data = &(struct clk_regmap_gate_data){
616 * b) CCF has a clock hand-off mechanism to make the sure the
635 .data = &(struct clk_regmap_gate_data){
661 .data = &(struct clk_regmap_gate_data){
687 .data = &(struct clk_regmap_gate_data){
702 .data = &(struct clk_regmap_div_data){
704 .shift = 12,
716 .data = &(struct meson_clk_mpll_data){
719 .shift = 0,
724 .shift = 25,
729 .shift = 16,
744 .data = &(struct meson_clk_mpll_data){
747 .shift = 0,
752 .shift = 15,
757 .shift = 16,
772 .data = &(struct clk_regmap_gate_data){
787 .index = -1,
795 .data = &(struct meson_clk_mpll_data){
798 .shift = 0,
803 .shift = 15,
808 .shift = 16,
823 .data = &(struct clk_regmap_gate_data){
837 .data = &(struct meson_clk_mpll_data){
840 .shift = 0,
845 .shift = 15,
850 .shift = 16,
865 .data = &(struct clk_regmap_gate_data){
890 .data = &(struct clk_regmap_mux_data){
893 .shift = 12,
910 .data = &(struct clk_regmap_div_data){
912 .shift = 0,
927 .data = &(struct clk_regmap_gate_data){
943 .data = &(struct clk_regmap_mux_data){
946 .shift = 9,
961 .data = &(struct clk_regmap_div_data){
963 .shift = 0,
978 .data = &(struct clk_regmap_gate_data){
995 * muxed by a glitch-free switch. The CCF can manage this glitch-free
996 * mux because it does top-to-bottom updates the each clock tree and
1012 .data = &(struct clk_regmap_mux_data){
1015 .shift = 9,
1033 .data = &(struct clk_regmap_div_data){
1035 .shift = 0,
1050 .data = &(struct clk_regmap_gate_data){
1066 .data = &(struct clk_regmap_mux_data){
1069 .shift = 25,
1087 .data = &(struct clk_regmap_div_data){
1089 .shift = 16,
1104 .data = &(struct clk_regmap_gate_data){
1125 .data = &(struct clk_regmap_mux_data){
1128 .shift = 31,
1140 .data = &(struct clk_regmap_mux_data){
1143 .shift = 9,
1160 .data = &(struct clk_regmap_div_data) {
1162 .shift = 0,
1178 .data = &(struct clk_regmap_gate_data){
1194 .data = &(struct clk_regmap_mux_data){
1197 .shift = 25,
1214 .data = &(struct clk_regmap_div_data){
1216 .shift = 16,
1232 .data = &(struct clk_regmap_gate_data){
1248 .data = &(struct clk_regmap_mux_data){
1251 .shift = 27,
1262 *The parent is specific to origin of the audio data. Let the
1276 { .name = "cts_slow_oscin", .index = -1 },
1282 .data = &(struct clk_regmap_mux_data){
1285 .shift = 16,
1297 .data = &(struct clk_regmap_div_data){
1299 .shift = 0,
1314 .data = &(struct clk_regmap_gate_data){
1345 .data = &(struct clk_regmap_mux_data){
1348 .shift = 9,
1360 .data = &(struct clk_regmap_div_data){
1362 .shift = 0,
1378 .data = &(struct clk_regmap_gate_data){
1395 .data = &(struct clk_regmap_mux_data){
1398 .shift = 25,
1410 .data = &(struct clk_regmap_div_data){
1412 .shift = 16,
1428 .data = &(struct clk_regmap_gate_data){
1445 .data = &(struct clk_regmap_mux_data){
1448 .shift = 9,
1460 .data = &(struct clk_regmap_div_data){
1462 .shift = 0,
1478 .data = &(struct clk_regmap_gate_data){
1503 .data = &(struct clk_regmap_mux_data){
1506 .shift = 9,
1522 .data = &(struct clk_regmap_div_data){
1524 .shift = 0,
1537 .data = &(struct clk_regmap_gate_data){
1551 .data = &(struct clk_regmap_mux_data){
1554 .shift = 25,
1570 .data = &(struct clk_regmap_div_data){
1572 .shift = 16,
1585 .data = &(struct clk_regmap_gate_data){
1599 .data = &(struct clk_regmap_mux_data){
1602 .shift = 31,
1630 .data = &(struct clk_regmap_mux_data){
1633 .shift = 9,
1649 .data = &(struct clk_regmap_div_data){
1651 .shift = 0,
1666 .data = &(struct clk_regmap_gate_data){
1682 .data = &(struct clk_regmap_mux_data){
1685 .shift = 25,
1701 .data = &(struct clk_regmap_div_data){
1703 .shift = 16,
1718 .data = &(struct clk_regmap_gate_data){
1734 .data = &(struct clk_regmap_mux_data){
1737 .shift = 31,
1756 .data = &(struct clk_regmap_gate_data){
1772 .data = &(struct meson_vid_pll_div_data){
1775 .shift = 0,
1780 .shift = 16,
1796 .index = -1,
1812 { .name = "hdmi_pll", .index = -1 },
1816 .data = &(struct clk_regmap_mux_data){
1819 .shift = 18,
1835 .data = &(struct clk_regmap_gate_data){
1861 .data = &(struct clk_regmap_mux_data){
1864 .shift = 16,
1881 .data = &(struct clk_regmap_mux_data){
1884 .shift = 16,
1901 .data = &(struct clk_regmap_gate_data){
1915 .data = &(struct clk_regmap_gate_data){
1929 .data = &(struct clk_regmap_div_data){
1931 .shift = 0,
1946 .data = &(struct clk_regmap_div_data){
1948 .shift = 0,
1963 .data = &(struct clk_regmap_gate_data){
1977 .data = &(struct clk_regmap_gate_data){
1991 .data = &(struct clk_regmap_gate_data){
2005 .data = &(struct clk_regmap_gate_data){
2019 .data = &(struct clk_regmap_gate_data){
2033 .data = &(struct clk_regmap_gate_data){
2047 .data = &(struct clk_regmap_gate_data){
2061 .data = &(struct clk_regmap_gate_data){
2075 .data = &(struct clk_regmap_gate_data){
2089 .data = &(struct clk_regmap_gate_data){
2103 .data = &(struct clk_regmap_gate_data){
2117 .data = &(struct clk_regmap_gate_data){
2249 .data = &(struct clk_regmap_mux_data){
2252 .shift = 28,
2265 .data = &(struct clk_regmap_mux_data){
2268 .shift = 20,
2281 .data = &(struct clk_regmap_mux_data){
2284 .shift = 28,
2312 .data = &(struct clk_regmap_mux_data){
2315 .shift = 16,
2334 .data = &(struct clk_regmap_gate_data){
2350 .data = &(struct clk_regmap_gate_data){
2366 .data = &(struct clk_regmap_gate_data){
2382 .data = &(struct clk_regmap_gate_data){
2407 .data = &(struct clk_regmap_mux_data){
2410 .shift = 9,
2423 .data = &(struct clk_regmap_div_data){
2425 .shift = 0,
2438 .data = &(struct clk_regmap_gate_data){
2461 .data = &(struct clk_regmap_mux_data){
2464 .shift = 9,
2477 .data = &(struct clk_regmap_div_data){
2479 .shift = 0,
2495 .data = &(struct clk_regmap_gate_data){
2511 .data = &(struct clk_regmap_mux_data){
2514 .shift = 25,
2527 .data = &(struct clk_regmap_div_data){
2529 .shift = 16,
2545 .data = &(struct clk_regmap_gate_data){
2577 .data = &(struct clk_regmap_mux_data){
2580 .shift = 12,
2598 .data = &(struct clk_regmap_div_data){
2600 .shift = 0,
2615 .data = &(struct clk_regmap_gate_data){
3551 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3552 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3560 .name = "gxbb-clkc",