Lines Matching +full:meson +full:- +full:display
1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-G12A Clock Controller Driver
13 #include <linux/clk-provider.h>
20 #include "clk-mpll.h"
21 #include "clk-pll.h"
22 #include "clk-regmap.h"
23 #include "clk-cpu-dyndiv.h"
24 #include "vid-pll-div.h"
26 #include "meson-eeclk.h"
29 #include <dt-bindings/clock/g12a-clkc.h>
310 * b) CCF has a clock hand-off mechanism to make the sure the
346 * b) CCF has a clock hand-off mechanism to make the sure the
390 /* This sub-tree is used a parking clock */
472 /* This sub-tree is used a parking clock */
619 /* This sub-tree is used a parking clock */
656 /* This sub-tree is used a parking clock */
958 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
959 * \- cpu_clk_postmux0 in g12a_cpu_clk_postmux_notifier_cb()
960 * \- cpu_clk_muxX_div in g12a_cpu_clk_postmux_notifier_cb()
961 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
962 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
964 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
965 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
969 clk_hw_set_parent(nb_data->cpu_clk_premux1, in g12a_cpu_clk_postmux_notifier_cb()
970 nb_data->xtal); in g12a_cpu_clk_postmux_notifier_cb()
973 clk_hw_set_parent(nb_data->cpu_clk_postmux1, in g12a_cpu_clk_postmux_notifier_cb()
974 nb_data->cpu_clk_premux1); in g12a_cpu_clk_postmux_notifier_cb()
977 clk_hw_set_parent(nb_data->cpu_clk_dyn, in g12a_cpu_clk_postmux_notifier_cb()
978 nb_data->cpu_clk_postmux1); in g12a_cpu_clk_postmux_notifier_cb()
983 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
984 * \- cpu_clk_postmux1 in g12a_cpu_clk_postmux_notifier_cb()
985 * \- cpu_clk_premux1 in g12a_cpu_clk_postmux_notifier_cb()
986 * \- xtal in g12a_cpu_clk_postmux_notifier_cb()
1001 clk_hw_set_parent(nb_data->cpu_clk_dyn, in g12a_cpu_clk_postmux_notifier_cb()
1002 nb_data->cpu_clk_postmux0); in g12a_cpu_clk_postmux_notifier_cb()
1007 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
1008 * \- cpu_clk_postmux0 in g12a_cpu_clk_postmux_notifier_cb()
1009 * \- cpu_clk_muxX_div in g12a_cpu_clk_postmux_notifier_cb()
1010 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
1011 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
1013 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
1014 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
1061 * \- sys_pll in g12a_sys_pll_notifier_cb()
1062 * \- sys_pll_dco in g12a_sys_pll_notifier_cb()
1066 clk_hw_set_parent(nb_data->cpu_clk, in g12a_sys_pll_notifier_cb()
1067 nb_data->cpu_clk_dyn); in g12a_sys_pll_notifier_cb()
1072 * \- cpu_clk_dyn in g12a_sys_pll_notifier_cb()
1073 * \- cpu_clk_dynX in g12a_sys_pll_notifier_cb()
1074 * \- cpu_clk_dynX_sel in g12a_sys_pll_notifier_cb()
1075 * \- cpu_clk_dynX_div in g12a_sys_pll_notifier_cb()
1076 * \- xtal/fclk_div2/fclk_div3 in g12a_sys_pll_notifier_cb()
1077 * \- xtal/fclk_div2/fclk_div3 in g12a_sys_pll_notifier_cb()
1091 clk_hw_set_parent(nb_data->cpu_clk, in g12a_sys_pll_notifier_cb()
1092 nb_data->sys_pll); in g12a_sys_pll_notifier_cb()
1098 * \- sys_pll in g12a_sys_pll_notifier_cb()
1099 * \- sys_pll_dco in g12a_sys_pll_notifier_cb()
1317 .index = -1,
1830 * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
1990 * Display directly handle hdmi pll registers ATM, we need
3903 * muxed by a glitch-free switch. The CCF can manage this glitch-free
3904 * mux because it does top-to-bottom updates the each clock tree and
5413 struct device *dev = &pdev->dev; in meson_g12b_dvfs_setup()
5490 struct device *dev = &pdev->dev; in meson_g12a_dvfs_setup()
5530 eeclkc_data = of_device_get_match_data(&pdev->dev); in meson_g12a_probe()
5532 return -EINVAL; in meson_g12a_probe()
5541 if (g12a_data->dvfs_setup) in meson_g12a_probe()
5542 return g12a_data->dvfs_setup(pdev); in meson_g12a_probe()
5587 .compatible = "amlogic,g12a-clkc",
5591 .compatible = "amlogic,g12b-clkc",
5595 .compatible = "amlogic,sm1-clkc",
5605 .name = "g12a-clkc",