Lines Matching +full:data +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-G12A Clock Controller Driver
13 #include <linux/clk-provider.h>
20 #include "clk-mpll.h"
21 #include "clk-pll.h"
22 #include "clk-regmap.h"
23 #include "clk-cpu-dyndiv.h"
24 #include "vid-pll-div.h"
26 #include "meson-eeclk.h"
29 #include <dt-bindings/clock/g12a-clkc.h>
32 .data = &(struct meson_clk_pll_data){
36 .width = 1,
41 .width = 8,
46 .width = 5,
51 .width = 17,
56 .width = 1,
61 .width = 1,
75 .data = &(struct clk_regmap_div_data){
78 .width = 2,
101 .data = &(struct meson_clk_pll_data){
105 .width = 1,
110 .width = 8,
115 .width = 5,
120 .width = 1,
125 .width = 1,
142 .data = &(struct clk_regmap_div_data){
145 .width = 3,
160 .data = &(struct meson_clk_pll_data){
164 .width = 1,
169 .width = 8,
174 .width = 5,
179 .width = 1,
184 .width = 1,
201 .data = &(struct clk_regmap_div_data){
204 .width = 3,
219 .data = &(struct clk_regmap_gate_data){
236 .data = &(struct clk_regmap_gate_data){
292 .data = &(struct clk_regmap_gate_data){
310 * b) CCF has a clock hand-off mechanism to make the sure the
329 .data = &(struct clk_regmap_gate_data){
346 * b) CCF has a clock hand-off mechanism to make the sure the
355 .data = &(struct clk_regmap_mux_data){
376 .data = &(struct clk_regmap_mux_data){
390 /* This sub-tree is used a parking clock */
397 .data = &(struct meson_clk_cpu_dyndiv_data){
401 .width = 6,
406 .width = 1,
422 .data = &(struct clk_regmap_mux_data){
442 .data = &(struct clk_regmap_div_data){
445 .width = 6,
459 .data = &(struct clk_regmap_mux_data){
472 /* This sub-tree is used a parking clock */
479 .data = &(struct clk_regmap_mux_data){
499 .data = &(struct clk_regmap_mux_data){
519 .data = &(struct clk_regmap_mux_data){
539 .data = &(struct clk_regmap_mux_data){
560 .data = &(struct meson_clk_cpu_dyndiv_data){
564 .width = 6,
569 .width = 1,
585 .data = &(struct clk_regmap_mux_data){
605 .data = &(struct clk_regmap_mux_data){
619 /* This sub-tree is used a parking clock */
626 .data = &(struct clk_regmap_div_data){
629 .width = 6,
643 .data = &(struct clk_regmap_mux_data){
656 /* This sub-tree is used a parking clock */
663 .data = &(struct clk_regmap_mux_data){
683 .data = &(struct clk_regmap_mux_data){
705 .data = &(struct clk_regmap_mux_data){
725 .data = &(struct clk_regmap_mux_data){
745 .data = &(struct clk_regmap_div_data){
748 .width = 6,
762 .data = &(struct clk_regmap_mux_data){
780 .data = &(struct clk_regmap_div_data){
783 .width = 6,
797 .data = &(struct clk_regmap_mux_data){
815 .data = &(struct clk_regmap_mux_data){
833 .data = &(struct clk_regmap_mux_data){
851 .data = &(struct clk_regmap_mux_data){
869 .data = &(struct clk_regmap_mux_data){
887 .data = &(struct clk_regmap_mux_data){
905 .data = &(struct clk_regmap_mux_data){
922 unsigned long event, void *data) in g12a_cpu_clk_mux_notifier_cb() argument
947 unsigned long event, void *data) in g12a_cpu_clk_postmux_notifier_cb() argument
958 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
959 * \- cpu_clk_postmux0 in g12a_cpu_clk_postmux_notifier_cb()
960 * \- cpu_clk_muxX_div in g12a_cpu_clk_postmux_notifier_cb()
961 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
962 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
964 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
965 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
969 clk_hw_set_parent(nb_data->cpu_clk_premux1, in g12a_cpu_clk_postmux_notifier_cb()
970 nb_data->xtal); in g12a_cpu_clk_postmux_notifier_cb()
973 clk_hw_set_parent(nb_data->cpu_clk_postmux1, in g12a_cpu_clk_postmux_notifier_cb()
974 nb_data->cpu_clk_premux1); in g12a_cpu_clk_postmux_notifier_cb()
977 clk_hw_set_parent(nb_data->cpu_clk_dyn, in g12a_cpu_clk_postmux_notifier_cb()
978 nb_data->cpu_clk_postmux1); in g12a_cpu_clk_postmux_notifier_cb()
983 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
984 * \- cpu_clk_postmux1 in g12a_cpu_clk_postmux_notifier_cb()
985 * \- cpu_clk_premux1 in g12a_cpu_clk_postmux_notifier_cb()
986 * \- xtal in g12a_cpu_clk_postmux_notifier_cb()
1001 clk_hw_set_parent(nb_data->cpu_clk_dyn, in g12a_cpu_clk_postmux_notifier_cb()
1002 nb_data->cpu_clk_postmux0); in g12a_cpu_clk_postmux_notifier_cb()
1007 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
1008 * \- cpu_clk_postmux0 in g12a_cpu_clk_postmux_notifier_cb()
1009 * \- cpu_clk_muxX_div in g12a_cpu_clk_postmux_notifier_cb()
1010 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
1011 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
1013 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
1014 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
1050 unsigned long event, void *data) in g12a_sys_pll_notifier_cb() argument
1061 * \- sys_pll in g12a_sys_pll_notifier_cb()
1062 * \- sys_pll_dco in g12a_sys_pll_notifier_cb()
1066 clk_hw_set_parent(nb_data->cpu_clk, in g12a_sys_pll_notifier_cb()
1067 nb_data->cpu_clk_dyn); in g12a_sys_pll_notifier_cb()
1072 * \- cpu_clk_dyn in g12a_sys_pll_notifier_cb()
1073 * \- cpu_clk_dynX in g12a_sys_pll_notifier_cb()
1074 * \- cpu_clk_dynX_sel in g12a_sys_pll_notifier_cb()
1075 * \- cpu_clk_dynX_div in g12a_sys_pll_notifier_cb()
1076 * \- xtal/fclk_div2/fclk_div3 in g12a_sys_pll_notifier_cb()
1077 * \- xtal/fclk_div2/fclk_div3 in g12a_sys_pll_notifier_cb()
1091 clk_hw_set_parent(nb_data->cpu_clk, in g12a_sys_pll_notifier_cb()
1092 nb_data->sys_pll); in g12a_sys_pll_notifier_cb()
1098 * \- sys_pll in g12a_sys_pll_notifier_cb()
1099 * \- sys_pll_dco in g12a_sys_pll_notifier_cb()
1133 .data = &(struct clk_regmap_gate_data){
1152 .data = &(struct clk_regmap_gate_data){
1197 .data = &(struct clk_regmap_div_data){
1200 .width = 3,
1212 .data = &(struct clk_regmap_gate_data){
1231 .data = &(struct clk_regmap_div_data){
1234 .width = 3,
1246 .data = &(struct clk_regmap_gate_data){
1265 .data = &(struct clk_regmap_div_data){
1268 .width = 3,
1280 .data = &(struct clk_regmap_gate_data){
1299 .data = &(struct clk_regmap_div_data){
1302 .width = 3,
1317 .index = -1,
1324 .data = &(struct clk_regmap_gate_data){
1435 .data = &(struct clk_regmap_mux_data){
1458 .data = &(struct clk_regmap_gate_data){
1478 .data = &(struct clk_regmap_mux_data){
1501 .data = &(struct clk_regmap_gate_data){
1521 .data = &(struct clk_regmap_mux_data){
1544 .data = &(struct clk_regmap_gate_data){
1564 .data = &(struct clk_regmap_mux_data){
1587 .data = &(struct clk_regmap_gate_data){
1624 .data = &(struct meson_clk_pll_data){
1628 .width = 1,
1633 .width = 8,
1638 .width = 5,
1643 .width = 17,
1648 .width = 1,
1653 .width = 1,
1670 .data = &(struct clk_regmap_div_data){
1673 .width = 3,
1689 .data = &(struct meson_clk_pll_data){
1693 .width = 1,
1698 .width = 8,
1703 .width = 5,
1708 .width = 17,
1713 .width = 1,
1718 .width = 1,
1734 .data = &(struct clk_regmap_div_data){
1737 .width = 3,
1764 .data = &(struct meson_clk_pll_data){
1768 .width = 1,
1773 .width = 8,
1778 .width = 5,
1783 .width = 17,
1788 .width = 1,
1793 .width = 1,
1811 .data = &(struct clk_regmap_div_data){
1814 .width = 2,
1856 .data = &(struct meson_clk_pll_data){
1860 .width = 1,
1865 .width = 8,
1870 .width = 5,
1875 .width = 12,
1880 .width = 1,
1885 .width = 1,
1916 .data = &(struct clk_regmap_div_data){
1919 .width = 5,
1950 .data = &(struct meson_clk_pll_data){
1954 .width = 1,
1959 .width = 8,
1964 .width = 5,
1969 .width = 16,
1974 .width = 1,
1979 .width = 1,
1998 .data = &(struct clk_regmap_div_data){
2001 .width = 2,
2016 .data = &(struct clk_regmap_div_data){
2019 .width = 2,
2034 .data = &(struct clk_regmap_div_data){
2037 .width = 2,
2063 .data = &(struct clk_regmap_gate_data){
2089 .data = &(struct clk_regmap_gate_data){
2115 .data = &(struct clk_regmap_gate_data){
2143 .data = &(struct clk_regmap_gate_data){
2171 .data = &(struct clk_regmap_mux_data){
2205 .data = &(struct meson_clk_mpll_data){
2209 .width = 14,
2214 .width = 1,
2219 .width = 9,
2224 .width = 1,
2240 .data = &(struct clk_regmap_gate_data){
2258 .data = &(struct meson_clk_mpll_data){
2262 .width = 14,
2267 .width = 1,
2272 .width = 9,
2277 .width = 1,
2293 .data = &(struct clk_regmap_gate_data){
2311 .data = &(struct meson_clk_mpll_data){
2315 .width = 14,
2320 .width = 1,
2325 .width = 9,
2330 .width = 1,
2346 .data = &(struct clk_regmap_gate_data){
2364 .data = &(struct meson_clk_mpll_data){
2368 .width = 14,
2373 .width = 1,
2378 .width = 9,
2383 .width = 1,
2399 .data = &(struct clk_regmap_gate_data){
2424 .data = &(struct clk_regmap_mux_data){
2439 .data = &(struct clk_regmap_div_data){
2442 .width = 7,
2456 .data = &(struct clk_regmap_gate_data){
2487 .data = &(struct clk_regmap_mux_data){
2502 .data = &(struct clk_regmap_div_data){
2505 .width = 7,
2519 .data = &(struct clk_regmap_gate_data){
2536 .data = &(struct clk_regmap_mux_data){
2551 .data = &(struct clk_regmap_div_data){
2554 .width = 7,
2568 .data = &(struct clk_regmap_gate_data){
2585 .data = &(struct clk_regmap_mux_data){
2600 .data = &(struct clk_regmap_div_data){
2603 .width = 7,
2617 .data = &(struct clk_regmap_gate_data){
2635 .data = &(struct meson_vid_pll_div_data){
2639 .width = 15,
2644 .width = 2,
2662 .data = &(struct clk_regmap_mux_data){
2681 .data = &(struct clk_regmap_gate_data){
2710 .data = &(struct clk_regmap_mux_data){
2725 .data = &(struct clk_regmap_div_data){
2728 .width = 7,
2740 .data = &(struct clk_regmap_gate_data){
2754 .data = &(struct clk_regmap_mux_data){
2769 .data = &(struct clk_regmap_div_data){
2772 .width = 7,
2784 .data = &(struct clk_regmap_gate_data){
2798 .data = &(struct clk_regmap_mux_data){
2832 .data = &(struct clk_regmap_mux_data){
2848 .data = &(struct clk_regmap_div_data){
2851 .width = 7,
2866 .data = &(struct clk_regmap_gate_data){
2882 .data = &(struct clk_regmap_mux_data){
2898 .data = &(struct clk_regmap_div_data){
2901 .width = 7,
2916 .data = &(struct clk_regmap_gate_data){
2932 .data = &(struct clk_regmap_mux_data){
2948 .data = &(struct clk_regmap_div_data){
2951 .width = 7,
2966 .data = &(struct clk_regmap_gate_data){
2995 .data = &(struct clk_regmap_mux_data){
3010 .data = &(struct clk_regmap_div_data){
3013 .width = 7,
3027 .data = &(struct clk_regmap_gate_data){
3043 .data = &(struct clk_regmap_mux_data){
3058 .data = &(struct clk_regmap_div_data){
3061 .width = 7,
3075 .data = &(struct clk_regmap_gate_data){
3091 .data = &(struct clk_regmap_mux_data){
3113 .data = &(struct clk_regmap_gate_data){
3138 .data = &(struct clk_regmap_mux_data){
3153 .data = &(struct clk_regmap_mux_data){
3168 .data = &(struct clk_regmap_gate_data){
3182 .data = &(struct clk_regmap_gate_data){
3195 .data = &(struct clk_regmap_div_data){
3198 .width = 8,
3212 .data = &(struct meson_vclk_div_data){
3216 .width = 8,
3221 .width = 1,
3226 .width = 1,
3242 .data = &(struct clk_regmap_gate_data){
3256 .data = &(struct meson_vclk_gate_data){
3260 .width = 1,
3265 .width = 1,
3278 .data = &(struct clk_regmap_gate_data){
3292 .data = &(struct clk_regmap_gate_data){
3306 .data = &(struct clk_regmap_gate_data){
3320 .data = &(struct clk_regmap_gate_data){
3334 .data = &(struct clk_regmap_gate_data){
3348 .data = &(struct clk_regmap_gate_data){
3362 .data = &(struct clk_regmap_gate_data){
3376 .data = &(struct clk_regmap_gate_data){
3390 .data = &(struct clk_regmap_gate_data){
3404 .data = &(struct clk_regmap_gate_data){
3540 .data = &(struct clk_regmap_mux_data){
3556 .data = &(struct clk_regmap_mux_data){
3572 .data = &(struct clk_regmap_mux_data){
3588 .data = &(struct clk_regmap_mux_data){
3619 .data = &(struct clk_regmap_mux_data){
3635 .data = &(struct clk_regmap_gate_data){
3651 .data = &(struct clk_regmap_gate_data){
3667 .data = &(struct clk_regmap_gate_data){
3683 .data = &(struct clk_regmap_gate_data){
3699 .data = &(struct clk_regmap_gate_data){
3728 .data = &(struct clk_regmap_mux_data){
3754 .data = &(struct clk_regmap_div_data){
3757 .width = 7,
3772 .data = &(struct clk_regmap_gate_data){
3801 .data = &(struct clk_regmap_mux_data){
3815 .data = &(struct clk_regmap_div_data){
3818 .width = 7,
3832 .data = &(struct clk_regmap_gate_data){
3857 .data = &(struct clk_regmap_mux_data){
3873 .data = &(struct clk_regmap_div_data){
3876 .width = 7,
3888 .data = &(struct clk_regmap_gate_data){
3903 * muxed by a glitch-free switch. The CCF can manage this glitch-free
3904 * mux because it does top-to-bottom updates the each clock tree and
3919 .data = &(struct clk_regmap_mux_data){
3940 .data = &(struct clk_regmap_div_data){
3943 .width = 7,
3957 .data = &(struct clk_regmap_gate_data){
3973 .data = &(struct clk_regmap_mux_data){
3994 .data = &(struct clk_regmap_div_data){
3997 .width = 7,
4011 .data = &(struct clk_regmap_gate_data){
4032 .data = &(struct clk_regmap_mux_data){
4047 .data = &(struct clk_regmap_div_data){
4050 .width = 8,
4063 .data = &(struct clk_regmap_gate_data){
4089 .data = &(struct clk_regmap_mux_data){
4103 .data = &(struct clk_regmap_div_data){
4106 .width = 6,
4120 .data = &(struct clk_regmap_gate_data){
4136 .data = &(struct clk_regmap_mux_data){
4150 .data = &(struct clk_regmap_div_data){
4153 .width = 6,
4167 .data = &(struct clk_regmap_gate_data){
4196 .data = &(struct clk_regmap_mux_data){
4210 .data = &(struct clk_regmap_div_data){
4213 .width = 7,
4227 .data = &(struct clk_regmap_gate_data){
4243 .data = &(struct clk_regmap_mux_data){
4257 .data = &(struct clk_regmap_div_data){
4260 .width = 7,
4274 .data = &(struct clk_regmap_gate_data){
5413 struct device *dev = &pdev->dev; in meson_g12b_dvfs_setup()
5490 struct device *dev = &pdev->dev; in meson_g12a_dvfs_setup()
5530 eeclkc_data = of_device_get_match_data(&pdev->dev); in meson_g12a_probe()
5532 return -EINVAL; in meson_g12a_probe()
5541 if (g12a_data->dvfs_setup) in meson_g12a_probe()
5542 return g12a_data->dvfs_setup(pdev); in meson_g12a_probe()
5587 .compatible = "amlogic,g12a-clkc",
5588 .data = &g12a_clkc_data.eeclkc_data
5591 .compatible = "amlogic,g12b-clkc",
5592 .data = &g12b_clkc_data.eeclkc_data
5595 .compatible = "amlogic,sm1-clkc",
5596 .data = &sm1_clkc_data.eeclkc_data
5605 .name = "g12a-clkc",