Lines Matching full:hw
173 .hw.init = &(struct clk_init_data){
190 .hw.init = &(struct clk_init_data){
194 &g12a_fixed_pll_dco.hw
238 .hw.init = &(struct clk_init_data){
257 .hw.init = &(struct clk_init_data){
261 &g12a_sys_pll_dco.hw
297 .hw.init = &(struct clk_init_data){
316 .hw.init = &(struct clk_init_data){
320 &g12b_sys1_pll_dco.hw
332 .hw.init = &(struct clk_init_data) {
335 .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
349 .hw.init = &(struct clk_init_data) {
353 &g12b_sys1_pll.hw
366 .hw.init = &(struct clk_init_data){
370 &g12a_sys_pll_div16_en.hw
379 .hw.init = &(struct clk_init_data){
383 &g12b_sys1_pll_div16_en.hw
442 .hw.init = &(struct clk_init_data){
460 .hw.init = &(struct clk_init_data){
464 &g12a_gp0_pll_dco.hw
504 .hw.init = &(struct clk_init_data){
524 .hw.init = &(struct clk_init_data){
528 &sm1_gp1_pll_dco.hw
583 .hw.init = &(struct clk_init_data){
601 .hw.init = &(struct clk_init_data){
605 &g12a_hifi_pll_dco.hw
674 .hw.init = &(struct clk_init_data){
687 .hw.init = &(struct clk_init_data){
691 &g12a_pcie_pll_dco.hw
707 .hw.init = &(struct clk_init_data){
711 &g12a_pcie_pll_dco_div2.hw
721 .hw.init = &(struct clk_init_data){
725 &g12a_pcie_pll_od.hw
765 .hw.init = &(struct clk_init_data){
787 .hw.init = &(struct clk_init_data){
791 &g12a_hdmi_pll_dco.hw
805 .hw.init = &(struct clk_init_data){
809 &g12a_hdmi_pll_od.hw
823 .hw.init = &(struct clk_init_data){
827 &g12a_hdmi_pll_od2.hw
837 .hw.init = &(struct clk_init_data){
840 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
850 .hw.init = &(struct clk_init_data){
854 &g12a_fclk_div2_div.hw
874 .hw.init = &(struct clk_init_data){
877 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
887 .hw.init = &(struct clk_init_data){
891 &g12a_fclk_div3_div.hw
911 .hw.init = &(struct clk_init_data){
914 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
924 .hw.init = &(struct clk_init_data){
928 &g12a_fclk_div4_div.hw
937 .hw.init = &(struct clk_init_data){
940 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
950 .hw.init = &(struct clk_init_data){
954 &g12a_fclk_div5_div.hw
963 .hw.init = &(struct clk_init_data){
966 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
976 .hw.init = &(struct clk_init_data){
980 &g12a_fclk_div7_div.hw
989 .hw.init = &(struct clk_init_data){
993 &g12a_fixed_pll_dco.hw
1004 .hw.init = &(struct clk_init_data){
1008 &g12a_fclk_div2p5_div.hw
1017 .hw.init = &(struct clk_init_data){
1021 &g12a_fixed_pll_dco.hw
1033 .hw.init = &(struct clk_init_data){
1038 { .hw = &g12a_mpll_50m_div.hw },
1047 .hw.init = &(struct clk_init_data){
1051 &g12a_fixed_pll_dco.hw
1065 .hw.init = &(struct clk_init_data){
1070 { .hw = &g12a_fclk_div2.hw },
1071 { .hw = &g12a_fclk_div3.hw },
1092 .hw.init = &(struct clk_init_data){
1096 &g12a_cpu_clk_dyn0_sel.hw
1111 .hw.init = &(struct clk_init_data){
1115 &g12a_cpu_clk_dyn0_sel.hw,
1116 &g12a_cpu_clk_dyn0_div.hw,
1130 .hw.init = &(struct clk_init_data){
1135 { .hw = &g12a_fclk_div2.hw },
1136 { .hw = &g12a_fclk_div3.hw },
1151 .hw.init = &(struct clk_init_data){
1155 &g12a_cpu_clk_dyn1_sel.hw
1168 .hw.init = &(struct clk_init_data){
1172 &g12a_cpu_clk_dyn1_sel.hw,
1173 &g12a_cpu_clk_dyn1_div.hw,
1189 .hw.init = &(struct clk_init_data){
1193 &g12a_cpu_clk_dyn0.hw,
1194 &g12a_cpu_clk_dyn1.hw,
1209 .hw.init = &(struct clk_init_data){
1213 &g12a_cpu_clk_dyn.hw,
1214 &g12a_sys_pll.hw,
1229 .hw.init = &(struct clk_init_data){
1233 &g12a_cpu_clk_dyn.hw,
1234 &g12b_sys1_pll.hw
1249 .hw.init = &(struct clk_init_data){
1254 { .hw = &g12a_fclk_div2.hw },
1255 { .hw = &g12a_fclk_div3.hw },
1276 .hw.init = &(struct clk_init_data){
1280 &g12b_cpub_clk_dyn0_sel.hw
1295 .hw.init = &(struct clk_init_data){
1299 &g12b_cpub_clk_dyn0_sel.hw,
1300 &g12b_cpub_clk_dyn0_div.hw
1314 .hw.init = &(struct clk_init_data){
1319 { .hw = &g12a_fclk_div2.hw },
1320 { .hw = &g12a_fclk_div3.hw },
1335 .hw.init = &(struct clk_init_data){
1339 &g12b_cpub_clk_dyn1_sel.hw
1352 .hw.init = &(struct clk_init_data){
1356 &g12b_cpub_clk_dyn1_sel.hw,
1357 &g12b_cpub_clk_dyn1_div.hw
1373 .hw.init = &(struct clk_init_data){
1377 &g12b_cpub_clk_dyn0.hw,
1378 &g12b_cpub_clk_dyn1.hw
1393 .hw.init = &(struct clk_init_data){
1397 &g12b_cpub_clk_dyn.hw,
1398 &g12a_sys_pll.hw
1412 .hw.init = &(struct clk_init_data){
1417 { .hw = &g12a_fclk_div2.hw },
1418 { .hw = &g12a_fclk_div3.hw },
1419 { .hw = &sm1_gp1_pll.hw },
1432 .hw.init = &(struct clk_init_data){
1436 &sm1_dsu_clk_dyn0_sel.hw
1449 .hw.init = &(struct clk_init_data){
1453 &sm1_dsu_clk_dyn0_sel.hw,
1454 &sm1_dsu_clk_dyn0_div.hw,
1467 .hw.init = &(struct clk_init_data){
1472 { .hw = &g12a_fclk_div2.hw },
1473 { .hw = &g12a_fclk_div3.hw },
1474 { .hw = &sm1_gp1_pll.hw },
1487 .hw.init = &(struct clk_init_data){
1491 &sm1_dsu_clk_dyn1_sel.hw
1504 .hw.init = &(struct clk_init_data){
1508 &sm1_dsu_clk_dyn1_sel.hw,
1509 &sm1_dsu_clk_dyn1_div.hw,
1522 .hw.init = &(struct clk_init_data){
1526 &sm1_dsu_clk_dyn0.hw,
1527 &sm1_dsu_clk_dyn1.hw,
1540 .hw.init = &(struct clk_init_data){
1544 &sm1_dsu_clk_dyn.hw,
1545 &g12a_sys_pll.hw,
1558 .hw.init = &(struct clk_init_data){
1562 &g12a_cpu_clk.hw,
1576 .hw.init = &(struct clk_init_data){
1580 &g12a_cpu_clk.hw,
1594 .hw.init = &(struct clk_init_data){
1598 &g12a_cpu_clk.hw,
1612 .hw.init = &(struct clk_init_data){
1616 &g12a_cpu_clk.hw,
1617 &sm1_dsu_final_clk.hw,
1729 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1730 .cpu_clk_postmux0 = &g12a_cpu_clk_dyn0.hw,
1731 .cpu_clk_postmux1 = &g12a_cpu_clk_dyn1.hw,
1732 .cpu_clk_premux1 = &g12a_cpu_clk_dyn1_sel.hw,
1737 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1738 .cpu_clk_postmux0 = &g12b_cpub_clk_dyn0.hw,
1739 .cpu_clk_postmux1 = &g12b_cpub_clk_dyn1.hw,
1740 .cpu_clk_premux1 = &g12b_cpub_clk_dyn1_sel.hw,
1812 .sys_pll = &g12a_sys_pll.hw,
1813 .cpu_clk = &g12a_cpu_clk.hw,
1814 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1820 .sys_pll = &g12b_sys1_pll.hw,
1821 .cpu_clk = &g12b_cpu_clk.hw,
1822 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1828 .sys_pll = &g12a_sys_pll.hw,
1829 .cpu_clk = &g12b_cpub_clk.hw,
1830 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1839 .hw.init = &(struct clk_init_data) {
1868 .hw.init = &(struct clk_init_data) {
1872 &g12b_cpub_clk.hw
1885 .hw.init = &(struct clk_init_data){
1889 &g12a_cpu_clk_div16_en.hw
1898 .hw.init = &(struct clk_init_data){
1902 &g12b_cpub_clk_div16_en.hw
1915 .hw.init = &(struct clk_init_data){
1931 .hw.init = &(struct clk_init_data) {
1935 &g12a_cpu_clk_apb_div.hw
1952 .hw.init = &(struct clk_init_data){
1968 .hw.init = &(struct clk_init_data) {
1972 &g12a_cpu_clk_atb_div.hw
1989 .hw.init = &(struct clk_init_data){
2005 .hw.init = &(struct clk_init_data) {
2009 &g12a_cpu_clk_axi_div.hw
2026 .hw.init = &(struct clk_init_data){
2042 .hw.init = &(struct clk_init_data) {
2046 &g12a_cpu_clk_trace_div.hw
2059 .hw.init = &(struct clk_init_data){
2063 &g12b_cpub_clk.hw
2072 .hw.init = &(struct clk_init_data){
2076 &g12b_cpub_clk.hw
2085 .hw.init = &(struct clk_init_data){
2089 &g12b_cpub_clk.hw
2098 .hw.init = &(struct clk_init_data){
2102 &g12b_cpub_clk.hw
2111 .hw.init = &(struct clk_init_data){
2115 &g12b_cpub_clk.hw
2124 .hw.init = &(struct clk_init_data){
2128 &g12b_cpub_clk.hw
2137 .hw.init = &(struct clk_init_data){
2141 &g12b_cpub_clk.hw
2149 &g12b_cpub_clk_div2.hw,
2150 &g12b_cpub_clk_div3.hw,
2151 &g12b_cpub_clk_div4.hw,
2152 &g12b_cpub_clk_div5.hw,
2153 &g12b_cpub_clk_div6.hw,
2154 &g12b_cpub_clk_div7.hw,
2155 &g12b_cpub_clk_div8.hw,
2165 .hw.init = &(struct clk_init_data){
2179 .hw.init = &(struct clk_init_data) {
2183 &g12b_cpub_clk_apb_sel.hw
2200 .hw.init = &(struct clk_init_data){
2214 .hw.init = &(struct clk_init_data) {
2218 &g12b_cpub_clk_atb_sel.hw
2235 .hw.init = &(struct clk_init_data){
2249 .hw.init = &(struct clk_init_data) {
2253 &g12b_cpub_clk_axi_sel.hw
2270 .hw.init = &(struct clk_init_data){
2284 .hw.init = &(struct clk_init_data) {
2288 &g12b_cpub_clk_trace_sel.hw
2327 .hw.init = &(struct clk_init_data){
2331 &g12a_mpll_prediv.hw
2342 .hw.init = &(struct clk_init_data){
2345 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
2380 .hw.init = &(struct clk_init_data){
2384 &g12a_mpll_prediv.hw
2395 .hw.init = &(struct clk_init_data){
2398 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
2433 .hw.init = &(struct clk_init_data){
2437 &g12a_mpll_prediv.hw
2448 .hw.init = &(struct clk_init_data){
2451 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
2486 .hw.init = &(struct clk_init_data){
2490 &g12a_mpll_prediv.hw
2501 .hw.init = &(struct clk_init_data){
2504 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
2514 { .hw = &g12a_fclk_div7.hw },
2515 { .hw = &g12a_mpll1.hw },
2516 { .hw = &g12a_mpll2.hw },
2517 { .hw = &g12a_fclk_div4.hw },
2518 { .hw = &g12a_fclk_div3.hw },
2519 { .hw = &g12a_fclk_div5.hw },
2529 .hw.init = &(struct clk_init_data){
2543 .hw.init = &(struct clk_init_data){
2547 &g12a_clk81_sel.hw
2559 .hw.init = &(struct clk_init_data){
2563 &g12a_clk81_div.hw
2572 { .hw = &g12a_fclk_div2.hw },
2573 { .hw = &g12a_fclk_div3.hw },
2574 { .hw = &g12a_fclk_div5.hw },
2575 { .hw = &g12a_fclk_div7.hw },
2591 .hw.init = &(struct clk_init_data) {
2606 .hw.init = &(struct clk_init_data) {
2610 &g12a_sd_emmc_a_clk0_sel.hw
2622 .hw.init = &(struct clk_init_data){
2626 &g12a_sd_emmc_a_clk0_div.hw
2640 .hw.init = &(struct clk_init_data) {
2655 .hw.init = &(struct clk_init_data) {
2659 &g12a_sd_emmc_b_clk0_sel.hw
2671 .hw.init = &(struct clk_init_data){
2675 &g12a_sd_emmc_b_clk0_div.hw
2689 .hw.init = &(struct clk_init_data) {
2704 .hw.init = &(struct clk_init_data) {
2708 &g12a_sd_emmc_c_clk0_sel.hw
2720 .hw.init = &(struct clk_init_data){
2724 &g12a_sd_emmc_c_clk0_div.hw
2746 .hw.init = &(struct clk_init_data) {
2749 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2756 &g12a_vid_pll_div.hw,
2757 &g12a_hdmi_pll.hw,
2766 .hw.init = &(struct clk_init_data){
2784 .hw.init = &(struct clk_init_data) {
2788 &g12a_vid_pll_sel.hw
2798 &g12a_fclk_div3.hw,
2799 &g12a_fclk_div4.hw,
2800 &g12a_fclk_div5.hw,
2801 &g12a_fclk_div7.hw,
2802 &g12a_mpll1.hw,
2803 &g12a_vid_pll.hw,
2804 &g12a_hifi_pll.hw,
2805 &g12a_gp0_pll.hw,
2814 .hw.init = &(struct clk_init_data){
2829 .hw.init = &(struct clk_init_data){
2832 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
2843 .hw.init = &(struct clk_init_data) {
2846 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
2858 .hw.init = &(struct clk_init_data){
2873 .hw.init = &(struct clk_init_data){
2876 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
2887 .hw.init = &(struct clk_init_data) {
2890 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
2902 .hw.init = &(struct clk_init_data){
2910 &g12a_vpu_0.hw,
2911 &g12a_vpu_1.hw,
2921 &g12a_fclk_div2p5.hw,
2922 &g12a_fclk_div3.hw,
2923 &g12a_fclk_div4.hw,
2924 &g12a_fclk_div5.hw,
2925 &g12a_fclk_div7.hw,
2926 &g12a_hifi_pll.hw,
2927 &g12a_gp0_pll.hw,
2937 .hw.init = &(struct clk_init_data){
2953 .hw.init = &(struct clk_init_data){
2957 &g12a_vdec_1_sel.hw
2969 .hw.init = &(struct clk_init_data) {
2973 &g12a_vdec_1_div.hw
2987 .hw.init = &(struct clk_init_data){
3003 .hw.init = &(struct clk_init_data){
3007 &g12a_vdec_hevcf_sel.hw
3019 .hw.init = &(struct clk_init_data) {
3023 &g12a_vdec_hevcf_div.hw
3037 .hw.init = &(struct clk_init_data){
3053 .hw.init = &(struct clk_init_data){
3057 &g12a_vdec_hevc_sel.hw
3069 .hw.init = &(struct clk_init_data) {
3073 &g12a_vdec_hevc_div.hw
3083 &g12a_fclk_div4.hw,
3084 &g12a_fclk_div3.hw,
3085 &g12a_fclk_div5.hw,
3086 &g12a_fclk_div7.hw,
3087 &g12a_mpll1.hw,
3088 &g12a_vid_pll.hw,
3089 &g12a_mpll2.hw,
3090 &g12a_fclk_div2p5.hw,
3099 .hw.init = &(struct clk_init_data){
3114 .hw.init = &(struct clk_init_data){
3118 &g12a_vapb_0_sel.hw
3130 .hw.init = &(struct clk_init_data) {
3134 &g12a_vapb_0_div.hw
3147 .hw.init = &(struct clk_init_data){
3162 .hw.init = &(struct clk_init_data){
3166 &g12a_vapb_1_sel.hw
3178 .hw.init = &(struct clk_init_data) {
3182 &g12a_vapb_1_div.hw
3195 .hw.init = &(struct clk_init_data){
3203 &g12a_vapb_0.hw,
3204 &g12a_vapb_1.hw,
3216 .hw.init = &(struct clk_init_data) {
3219 .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
3226 &g12a_vid_pll.hw,
3227 &g12a_gp0_pll.hw,
3228 &g12a_hifi_pll.hw,
3229 &g12a_mpll1.hw,
3230 &g12a_fclk_div3.hw,
3231 &g12a_fclk_div4.hw,
3232 &g12a_fclk_div5.hw,
3233 &g12a_fclk_div7.hw,
3242 .hw.init = &(struct clk_init_data){
3257 .hw.init = &(struct clk_init_data){
3271 .hw.init = &(struct clk_init_data) {
3274 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
3285 .hw.init = &(struct clk_init_data) {
3288 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
3299 .hw.init = &(struct clk_init_data){
3303 &g12a_vclk_input.hw
3329 .hw.init = &(struct clk_init_data){
3333 &g12a_vclk2_input.hw
3345 .hw.init = &(struct clk_init_data) {
3348 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
3367 .hw.init = &(struct clk_init_data) {
3370 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
3381 .hw.init = &(struct clk_init_data) {
3384 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3395 .hw.init = &(struct clk_init_data) {
3398 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3409 .hw.init = &(struct clk_init_data) {
3412 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3423 .hw.init = &(struct clk_init_data) {
3426 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3437 .hw.init = &(struct clk_init_data) {
3440 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3451 .hw.init = &(struct clk_init_data) {
3454 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3465 .hw.init = &(struct clk_init_data) {
3468 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3479 .hw.init = &(struct clk_init_data) {
3482 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3493 .hw.init = &(struct clk_init_data) {
3496 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3507 .hw.init = &(struct clk_init_data) {
3510 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3519 .hw.init = &(struct clk_init_data){
3523 &g12a_vclk_div2_en.hw
3532 .hw.init = &(struct clk_init_data){
3536 &g12a_vclk_div4_en.hw
3545 .hw.init = &(struct clk_init_data){
3549 &g12a_vclk_div6_en.hw
3558 .hw.init = &(struct clk_init_data){
3562 &g12a_vclk_div12_en.hw
3571 .hw.init = &(struct clk_init_data){
3575 &g12a_vclk2_div2_en.hw
3585 .hw.init = &(struct clk_init_data){
3589 &g12a_vclk2_div4_en.hw
3599 .hw.init = &(struct clk_init_data){
3603 &g12a_vclk2_div6_en.hw
3613 .hw.init = &(struct clk_init_data){
3617 &g12a_vclk2_div12_en.hw
3626 &g12a_vclk_div1.hw,
3627 &g12a_vclk_div2.hw,
3628 &g12a_vclk_div4.hw,
3629 &g12a_vclk_div6.hw,
3630 &g12a_vclk_div12.hw,
3631 &g12a_vclk2_div1.hw,
3632 &g12a_vclk2_div2.hw,
3633 &g12a_vclk2_div4.hw,
3634 &g12a_vclk2_div6.hw,
3635 &g12a_vclk2_div12.hw,
3645 .hw.init = &(struct clk_init_data){
3661 .hw.init = &(struct clk_init_data){
3677 .hw.init = &(struct clk_init_data){
3693 .hw.init = &(struct clk_init_data){
3705 &g12a_vclk_div1.hw,
3706 &g12a_vclk_div2.hw,
3707 &g12a_vclk_div4.hw,
3708 &g12a_vclk_div6.hw,
3709 &g12a_vclk_div12.hw,
3710 &g12a_vclk2_div1.hw,
3711 &g12a_vclk2_div2.hw,
3712 &g12a_vclk2_div4.hw,
3713 &g12a_vclk2_div6.hw,
3714 &g12a_vclk2_div12.hw,
3724 .hw.init = &(struct clk_init_data){
3738 .hw.init = &(struct clk_init_data) {
3742 &g12a_cts_enci_sel.hw
3754 .hw.init = &(struct clk_init_data) {
3758 &g12a_cts_encp_sel.hw
3770 .hw.init = &(struct clk_init_data) {
3774 &g12a_cts_encl_sel.hw
3786 .hw.init = &(struct clk_init_data) {
3790 &g12a_cts_vdac_sel.hw
3802 .hw.init = &(struct clk_init_data) {
3806 &g12a_hdmi_tx_sel.hw
3816 &g12a_vid_pll.hw,
3817 &g12a_gp0_pll.hw,
3818 &g12a_hifi_pll.hw,
3819 &g12a_mpll1.hw,
3820 &g12a_fclk_div2.hw,
3821 &g12a_fclk_div2p5.hw,
3822 &g12a_fclk_div3.hw,
3823 &g12a_fclk_div7.hw,
3833 .hw.init = &(struct clk_init_data){
3859 .hw.init = &(struct clk_init_data){
3863 &g12a_mipi_dsi_pxclk_sel.hw
3875 .hw.init = &(struct clk_init_data) {
3879 &g12a_mipi_dsi_pxclk_div.hw
3890 { .hw = &g12a_gp0_pll.hw },
3891 { .hw = &g12a_hifi_pll.hw },
3892 { .hw = &g12a_fclk_div2p5.hw },
3893 { .hw = &g12a_fclk_div3.hw },
3894 { .hw = &g12a_fclk_div4.hw },
3895 { .hw = &g12a_fclk_div5.hw },
3896 { .hw = &g12a_fclk_div7.hw },
3905 .hw.init = &(struct clk_init_data){
3919 .hw.init = &(struct clk_init_data){
3923 &g12b_mipi_isp_sel.hw
3935 .hw.init = &(struct clk_init_data) {
3939 &g12b_mipi_isp_div.hw
3950 { .hw = &g12a_fclk_div4.hw },
3951 { .hw = &g12a_fclk_div3.hw },
3952 { .hw = &g12a_fclk_div5.hw },
3962 .hw.init = &(struct clk_init_data){
3977 .hw.init = &(struct clk_init_data){
3980 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
3991 .hw.init = &(struct clk_init_data) {
3994 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
4008 { .hw = &g12a_gp0_pll.hw },
4009 { .hw = &g12a_hifi_pll.hw },
4010 { .hw = &g12a_fclk_div2p5.hw },
4011 { .hw = &g12a_fclk_div3.hw },
4012 { .hw = &g12a_fclk_div4.hw },
4013 { .hw = &g12a_fclk_div5.hw },
4014 { .hw = &g12a_fclk_div7.hw },
4023 .hw.init = &(struct clk_init_data){
4044 .hw.init = &(struct clk_init_data){
4048 &g12a_mali_0_sel.hw
4060 .hw.init = &(struct clk_init_data){
4064 &g12a_mali_0_div.hw
4077 .hw.init = &(struct clk_init_data){
4098 .hw.init = &(struct clk_init_data){
4102 &g12a_mali_1_sel.hw
4114 .hw.init = &(struct clk_init_data){
4118 &g12a_mali_1_div.hw
4131 .hw.init = &(struct clk_init_data){
4135 &g12a_mali_0.hw,
4136 &g12a_mali_1.hw,
4149 .hw.init = &(struct clk_init_data){
4164 .hw.init = &(struct clk_init_data){
4168 &g12a_ts_div.hw
4178 { .hw = &g12a_clk81.hw },
4179 { .hw = &g12a_fclk_div4.hw },
4180 { .hw = &g12a_fclk_div3.hw },
4181 { .hw = &g12a_fclk_div2.hw },
4182 { .hw = &g12a_fclk_div5.hw },
4183 { .hw = &g12a_fclk_div7.hw },
4192 .hw.init = &(struct clk_init_data){
4206 .hw.init = &(struct clk_init_data){
4210 &g12a_spicc0_sclk_sel.hw
4222 .hw.init = &(struct clk_init_data){
4226 &g12a_spicc0_sclk_div.hw
4239 .hw.init = &(struct clk_init_data){
4253 .hw.init = &(struct clk_init_data){
4257 &g12a_spicc1_sclk_sel.hw
4269 .hw.init = &(struct clk_init_data){
4273 &g12a_spicc1_sclk_div.hw
4284 { .hw = &g12a_gp0_pll.hw, },
4285 { .hw = &g12a_hifi_pll.hw, },
4286 { .hw = &g12a_fclk_div2p5.hw, },
4287 { .hw = &g12a_fclk_div3.hw, },
4288 { .hw = &g12a_fclk_div4.hw, },
4289 { .hw = &g12a_fclk_div5.hw, },
4290 { .hw = &g12a_fclk_div7.hw },
4299 .hw.init = &(struct clk_init_data){
4313 .hw.init = &(struct clk_init_data){
4317 &sm1_nna_axi_clk_sel.hw
4329 .hw.init = &(struct clk_init_data){
4333 &sm1_nna_axi_clk_div.hw
4346 .hw.init = &(struct clk_init_data){
4360 .hw.init = &(struct clk_init_data){
4364 &sm1_nna_core_clk_sel.hw
4376 .hw.init = &(struct clk_init_data){
4380 &sm1_nna_core_clk_div.hw
4387 static const struct clk_parent_data g12a_pclk_parents = { .hw = &g12a_clk81.hw };
4485 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4486 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4487 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4488 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4489 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4490 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4491 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4492 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4493 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4494 [CLKID_MPEG_SEL] = &g12a_clk81_sel.hw,
4495 [CLKID_MPEG_DIV] = &g12a_clk81_div.hw,
4496 [CLKID_CLK81] = &g12a_clk81.hw,
4497 [CLKID_MPLL0] = &g12a_mpll0.hw,
4498 [CLKID_MPLL1] = &g12a_mpll1.hw,
4499 [CLKID_MPLL2] = &g12a_mpll2.hw,
4500 [CLKID_MPLL3] = &g12a_mpll3.hw,
4501 [CLKID_DDR] = &g12a_ddr.hw,
4502 [CLKID_DOS] = &g12a_dos.hw,
4503 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4504 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4505 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4506 [CLKID_ISA] = &g12a_isa.hw,
4507 [CLKID_PL301] = &g12a_pl301.hw,
4508 [CLKID_PERIPHS] = &g12a_periphs.hw,
4509 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4510 [CLKID_I2C] = &g12a_i2c.hw,
4511 [CLKID_SANA] = &g12a_sana.hw,
4512 [CLKID_SD] = &g12a_sd.hw,
4513 [CLKID_RNG0] = &g12a_rng0.hw,
4514 [CLKID_UART0] = &g12a_uart0.hw,
4515 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4516 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4517 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4518 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4519 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4520 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4521 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4522 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4523 [CLKID_AUDIO] = &g12a_audio.hw,
4524 [CLKID_ETH] = &g12a_eth_core.hw,
4525 [CLKID_DEMUX] = &g12a_demux.hw,
4526 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4527 [CLKID_ADC] = &g12a_adc.hw,
4528 [CLKID_UART1] = &g12a_uart1.hw,
4529 [CLKID_G2D] = &g12a_g2d.hw,
4530 [CLKID_RESET] = &g12a_reset.hw,
4531 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4532 [CLKID_PARSER] = &g12a_parser.hw,
4533 [CLKID_USB] = &g12a_usb_general.hw,
4534 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4535 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4536 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4537 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4538 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4539 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4540 [CLKID_BT656] = &g12a_bt656.hw,
4541 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4542 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4543 [CLKID_UART2] = &g12a_uart2.hw,
4544 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4545 [CLKID_GIC] = &g12a_gic.hw,
4546 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4547 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4548 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4549 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4550 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4551 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4552 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4553 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4554 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4555 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4556 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4557 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4558 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4559 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4560 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4561 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4562 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4563 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4564 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4565 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4566 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4567 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4568 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4569 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4570 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4571 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4572 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4573 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4574 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4575 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4576 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4577 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4578 [CLKID_ENC480P] = &g12a_enc480p.hw,
4579 [CLKID_RNG1] = &g12a_rng1.hw,
4580 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4581 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4582 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4583 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4584 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4585 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4586 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4587 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4588 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4589 [CLKID_DMA] = &g12a_dma.hw,
4590 [CLKID_EFUSE] = &g12a_efuse.hw,
4591 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4592 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4593 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4594 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4595 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4596 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4597 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4598 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4599 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4600 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4601 [CLKID_VPU] = &g12a_vpu.hw,
4602 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4603 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4604 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4605 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4606 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4607 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4608 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4609 [CLKID_VAPB] = &g12a_vapb.hw,
4610 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4611 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4612 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4613 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4614 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4615 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4616 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4617 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4618 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4619 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4620 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4621 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4622 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4623 [CLKID_VCLK] = &g12a_vclk.hw,
4624 [CLKID_VCLK2] = &g12a_vclk2.hw,
4625 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4626 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4627 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4628 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4629 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4630 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4631 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4632 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4633 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4634 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4635 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4636 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4637 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4638 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4639 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4640 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4641 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4642 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4643 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4644 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4645 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
4646 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4647 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4648 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4649 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4650 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
4651 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4652 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4653 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4654 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4655 [CLKID_HDMI] = &g12a_hdmi.hw,
4656 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4657 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4658 [CLKID_MALI_0] = &g12a_mali_0.hw,
4659 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4660 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4661 [CLKID_MALI_1] = &g12a_mali_1.hw,
4662 [CLKID_MALI] = &g12a_mali.hw,
4663 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4664 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4665 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4666 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4667 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_dyn0_sel.hw,
4668 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_dyn0_div.hw,
4669 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_dyn0.hw,
4670 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_dyn1_sel.hw,
4671 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_dyn1_div.hw,
4672 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_dyn1.hw,
4673 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4674 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4675 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4676 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4677 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4678 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4679 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4680 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4681 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4682 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4683 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4684 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4685 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4686 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4687 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4688 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4689 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4690 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4691 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4692 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4693 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4694 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4695 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4696 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4697 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4698 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4699 [CLKID_TS] = &g12a_ts.hw,
4700 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4701 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4702 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4703 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4704 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4705 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4706 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
4707 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
4708 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
4712 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4713 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4714 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4715 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4716 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4717 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4718 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4719 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4720 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4721 [CLKID_MPEG_SEL] = &g12a_clk81_sel.hw,
4722 [CLKID_MPEG_DIV] = &g12a_clk81_div.hw,
4723 [CLKID_CLK81] = &g12a_clk81.hw,
4724 [CLKID_MPLL0] = &g12a_mpll0.hw,
4725 [CLKID_MPLL1] = &g12a_mpll1.hw,
4726 [CLKID_MPLL2] = &g12a_mpll2.hw,
4727 [CLKID_MPLL3] = &g12a_mpll3.hw,
4728 [CLKID_DDR] = &g12a_ddr.hw,
4729 [CLKID_DOS] = &g12a_dos.hw,
4730 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4731 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4732 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4733 [CLKID_ISA] = &g12a_isa.hw,
4734 [CLKID_PL301] = &g12a_pl301.hw,
4735 [CLKID_PERIPHS] = &g12a_periphs.hw,
4736 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4737 [CLKID_I2C] = &g12a_i2c.hw,
4738 [CLKID_SANA] = &g12a_sana.hw,
4739 [CLKID_SD] = &g12a_sd.hw,
4740 [CLKID_RNG0] = &g12a_rng0.hw,
4741 [CLKID_UART0] = &g12a_uart0.hw,
4742 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4743 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4744 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4745 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4746 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4747 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4748 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4749 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4750 [CLKID_AUDIO] = &g12a_audio.hw,
4751 [CLKID_ETH] = &g12a_eth_core.hw,
4752 [CLKID_DEMUX] = &g12a_demux.hw,
4753 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4754 [CLKID_ADC] = &g12a_adc.hw,
4755 [CLKID_UART1] = &g12a_uart1.hw,
4756 [CLKID_G2D] = &g12a_g2d.hw,
4757 [CLKID_RESET] = &g12a_reset.hw,
4758 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4759 [CLKID_PARSER] = &g12a_parser.hw,
4760 [CLKID_USB] = &g12a_usb_general.hw,
4761 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4762 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4763 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4764 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4765 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4766 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4767 [CLKID_BT656] = &g12a_bt656.hw,
4768 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4769 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4770 [CLKID_UART2] = &g12a_uart2.hw,
4771 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4772 [CLKID_GIC] = &g12a_gic.hw,
4773 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4774 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4775 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4776 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4777 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4778 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4779 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4780 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4781 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4782 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4783 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4784 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4785 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4786 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4787 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4788 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4789 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4790 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4791 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4792 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4793 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4794 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4795 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4796 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4797 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4798 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4799 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4800 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4801 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4802 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4803 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4804 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4805 [CLKID_ENC480P] = &g12a_enc480p.hw,
4806 [CLKID_RNG1] = &g12a_rng1.hw,
4807 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4808 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4809 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4810 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4811 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4812 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4813 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4814 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4815 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4816 [CLKID_DMA] = &g12a_dma.hw,
4817 [CLKID_EFUSE] = &g12a_efuse.hw,
4818 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4819 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4820 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4821 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4822 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4823 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4824 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4825 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4826 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4827 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4828 [CLKID_VPU] = &g12a_vpu.hw,
4829 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4830 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4831 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4832 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4833 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4834 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4835 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4836 [CLKID_VAPB] = &g12a_vapb.hw,
4837 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4838 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4839 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4840 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4841 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4842 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4843 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4844 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4845 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4846 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4847 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4848 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4849 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4850 [CLKID_VCLK] = &g12a_vclk.hw,
4851 [CLKID_VCLK2] = &g12a_vclk2.hw,
4852 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4853 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4854 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4855 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4856 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4857 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4858 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4859 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4860 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4861 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4862 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4863 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4864 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4865 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4866 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4867 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4868 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4869 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4870 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4871 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4872 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
4873 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4874 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4875 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4876 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4877 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
4878 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4879 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4880 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4881 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4882 [CLKID_HDMI] = &g12a_hdmi.hw,
4883 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4884 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4885 [CLKID_MALI_0] = &g12a_mali_0.hw,
4886 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4887 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4888 [CLKID_MALI_1] = &g12a_mali_1.hw,
4889 [CLKID_MALI] = &g12a_mali.hw,
4890 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4891 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4892 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4893 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4894 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_dyn0_sel.hw,
4895 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_dyn0_div.hw,
4896 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_dyn0.hw,
4897 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_dyn1_sel.hw,
4898 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_dyn1_div.hw,
4899 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_dyn1.hw,
4900 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4901 [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
4902 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4903 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4904 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4905 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4906 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4907 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4908 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4909 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4910 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4911 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4912 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4913 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4914 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4915 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4916 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4917 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4918 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4919 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4920 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4921 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4922 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4923 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4924 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4925 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4926 [CLKID_TS] = &g12a_ts.hw,
4927 [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
4928 [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
4929 [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
4930 [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
4931 [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_dyn0_sel.hw,
4932 [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_dyn0_div.hw,
4933 [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_dyn0.hw,
4934 [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_dyn1_sel.hw,
4935 [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_dyn1_div.hw,
4936 [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_dyn1.hw,
4937 [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
4938 [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
4939 [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
4940 [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
4941 [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
4942 [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
4943 [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
4944 [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
4945 [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
4946 [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
4947 [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
4948 [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
4949 [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
4950 [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
4951 [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
4952 [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
4953 [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
4954 [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
4955 [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
4956 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4957 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4958 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4959 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4960 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4961 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4962 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
4963 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
4964 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
4965 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
4966 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
4967 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
4968 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
4969 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
4970 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
4971 [CLKID_MIPI_ISP_SEL] = &g12b_mipi_isp_sel.hw,
4972 [CLKID_MIPI_ISP_DIV] = &g12b_mipi_isp_div.hw,
4973 [CLKID_MIPI_ISP] = &g12b_mipi_isp.hw,
4974 [CLKID_MIPI_ISP_GATE] = &g12b_mipi_isp_gate.hw,
4975 [CLKID_MIPI_ISP_CSI_PHY0] = &g12b_csi_phy0.hw,
4976 [CLKID_MIPI_ISP_CSI_PHY1] = &g12b_csi_phy1.hw,
4980 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4981 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4982 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4983 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4984 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4985 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4986 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4987 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4988 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4989 [CLKID_MPEG_SEL] = &g12a_clk81_sel.hw,
4990 [CLKID_MPEG_DIV] = &g12a_clk81_div.hw,
4991 [CLKID_CLK81] = &g12a_clk81.hw,
4992 [CLKID_MPLL0] = &g12a_mpll0.hw,
4993 [CLKID_MPLL1] = &g12a_mpll1.hw,
4994 [CLKID_MPLL2] = &g12a_mpll2.hw,
4995 [CLKID_MPLL3] = &g12a_mpll3.hw,
4996 [CLKID_DDR] = &g12a_ddr.hw,
4997 [CLKID_DOS] = &g12a_dos.hw,
4998 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4999 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
5000 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
5001 [CLKID_ISA] = &g12a_isa.hw,
5002 [CLKID_PL301] = &g12a_pl301.hw,
5003 [CLKID_PERIPHS] = &g12a_periphs.hw,
5004 [CLKID_SPICC0] = &g12a_spicc_0.hw,
5005 [CLKID_I2C] = &g12a_i2c.hw,
5006 [CLKID_SANA] = &g12a_sana.hw,
5007 [CLKID_SD] = &g12a_sd.hw,
5008 [CLKID_RNG0] = &g12a_rng0.hw,
5009 [CLKID_UART0] = &g12a_uart0.hw,
5010 [CLKID_SPICC1] = &g12a_spicc_1.hw,
5011 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
5012 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
5013 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
5014 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
5015 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
5016 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
5017 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
5018 [CLKID_AUDIO] = &g12a_audio.hw,
5019 [CLKID_ETH] = &g12a_eth_core.hw,
5020 [CLKID_DEMUX] = &g12a_demux.hw,
5021 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
5022 [CLKID_ADC] = &g12a_adc.hw,
5023 [CLKID_UART1] = &g12a_uart1.hw,
5024 [CLKID_G2D] = &g12a_g2d.hw,
5025 [CLKID_RESET] = &g12a_reset.hw,
5026 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
5027 [CLKID_PARSER] = &g12a_parser.hw,
5028 [CLKID_USB] = &g12a_usb_general.hw,
5029 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
5030 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
5031 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
5032 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
5033 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
5034 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
5035 [CLKID_BT656] = &g12a_bt656.hw,
5036 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
5037 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
5038 [CLKID_UART2] = &g12a_uart2.hw,
5039 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
5040 [CLKID_GIC] = &g12a_gic.hw,
5041 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
5042 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
5043 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
5044 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
5045 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
5046 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
5047 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
5048 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
5049 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
5050 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
5051 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
5052 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
5053 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
5054 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
5055 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
5056 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
5057 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
5058 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
5059 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
5060 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
5061 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
5062 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
5063 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
5064 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
5065 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
5066 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
5067 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
5068 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
5069 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
5070 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
5071 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
5072 [CLKID_IEC958] = &g12a_iec958_gate.hw,
5073 [CLKID_ENC480P] = &g12a_enc480p.hw,
5074 [CLKID_RNG1] = &g12a_rng1.hw,
5075 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
5076 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
5077 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
5078 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
5079 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
5080 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
5081 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
5082 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
5083 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
5084 [CLKID_DMA] = &g12a_dma.hw,
5085 [CLKID_EFUSE] = &g12a_efuse.hw,
5086 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
5087 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
5088 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
5089 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
5090 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
5091 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
5092 [CLKID_VPU_0] = &g12a_vpu_0.hw,
5093 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
5094 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
5095 [CLKID_VPU_1] = &g12a_vpu_1.hw,
5096 [CLKID_VPU] = &g12a_vpu.hw,
5097 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
5098 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
5099 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
5100 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
5101 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
5102 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
5103 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
5104 [CLKID_VAPB] = &g12a_vapb.hw,
5105 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
5106 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
5107 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
5108 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
5109 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
5110 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
5111 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
5112 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
5113 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
5114 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
5115 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
5116 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
5117 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
5118 [CLKID_VCLK] = &g12a_vclk.hw,
5119 [CLKID_VCLK2] = &g12a_vclk2.hw,
5120 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
5121 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
5122 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
5123 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
5124 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
5125 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
5126 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
5127 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
5128 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
5129 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
5130 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
5131 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
5132 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
5133 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
5134 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
5135 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
5136 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
5137 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
5138 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
5139 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
5140 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
5141 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
5142 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
5143 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
5144 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
5145 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
5146 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
5147 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
5148 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
5149 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
5150 [CLKID_HDMI] = &g12a_hdmi.hw,
5151 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
5152 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
5153 [CLKID_MALI_0] = &g12a_mali_0.hw,
5154 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
5155 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
5156 [CLKID_MALI_1] = &g12a_mali_1.hw,
5157 [CLKID_MALI] = &g12a_mali.hw,
5158 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
5159 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
5160 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
5161 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
5162 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_dyn0_sel.hw,
5163 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_dyn0_div.hw,
5164 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_dyn0.hw,
5165 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_dyn1_sel.hw,
5166 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_dyn1_div.hw,
5167 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_dyn1.hw,
5168 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
5169 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
5170 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
5171 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
5172 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
5173 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
5174 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
5175 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
5176 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
5177 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
5178 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
5179 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
5180 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
5181 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
5182 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
5183 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
5184 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
5185 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
5186 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
5187 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
5188 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
5189 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
5190 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
5191 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
5192 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
5193 [CLKID_TS_DIV] = &g12a_ts_div.hw,
5194 [CLKID_TS] = &g12a_ts.hw,
5195 [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
5196 [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
5197 [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_dyn0_sel.hw,
5198 [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_dyn0_div.hw,
5199 [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_dyn0.hw,
5200 [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_dyn1_sel.hw,
5201 [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_dyn1_div.hw,
5202 [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_dyn1.hw,
5203 [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
5204 [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
5205 [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
5206 [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
5207 [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
5208 [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
5209 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
5210 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
5211 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
5212 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
5213 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
5214 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
5215 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
5216 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
5217 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
5218 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
5219 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
5220 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
5221 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
5222 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
5223 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
5242 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn0.hw, in g12a_dvfs_setup_common()
5252 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn.hw, in g12a_dvfs_setup_common()
5279 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw, in g12b_dvfs_setup()
5289 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_sys1_pll.hw, in g12b_dvfs_setup()
5302 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn0.hw, in g12b_dvfs_setup()
5312 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw, in g12b_dvfs_setup()
5322 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk.hw, DVFS_CON_ID); in g12b_dvfs_setup()
5331 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID); in g12b_dvfs_setup()
5354 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk.hw, DVFS_CON_ID); in g12a_dvfs_setup()
5363 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID); in g12a_dvfs_setup()