Lines Matching full:static
60 static struct clk_regmap c3_rtc_xtal_clkin = {
75 static const struct meson_clk_dualdiv_param c3_rtc_32k_div_table[] = {
80 static struct clk_regmap c3_rtc_32k_div = {
119 static const struct clk_parent_data c3_rtc_32k_parents[] = {
124 static struct clk_regmap c3_rtc_32k_sel = {
139 static struct clk_regmap c3_rtc_32k = {
155 static const struct clk_parent_data c3_rtc_clk_parents[] = {
161 static struct clk_regmap c3_rtc_clk = {
176 static const struct clk_parent_data c3_sys_pclk_parents = { .fw_name = "sysclk" };
184 static C3_SYS_PCLK(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0);
185 static C3_SYS_PCLK(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0);
186 static C3_SYS_PCLK(sys_pad_ctrl, SYS_CLK_EN0_REG0, 4, 0);
187 static C3_SYS_PCLK(sys_ctrl, SYS_CLK_EN0_REG0, 5, 0);
188 static C3_SYS_PCLK(sys_ts_pll, SYS_CLK_EN0_REG0, 6, 0);
194 static C3_SYS_PCLK(sys_dev_arb, SYS_CLK_EN0_REG0, 7, 0);
200 static C3_SYS_PCLK_RO(sys_mmc_pclk, SYS_CLK_EN0_REG0, 8);
206 static C3_SYS_PCLK(sys_cpu_ctrl, SYS_CLK_EN0_REG0, 11, CLK_IS_CRITICAL);
207 static C3_SYS_PCLK(sys_jtag_ctrl, SYS_CLK_EN0_REG0, 12, 0);
208 static C3_SYS_PCLK(sys_ir_ctrl, SYS_CLK_EN0_REG0, 13, 0);
216 static C3_SYS_PCLK(sys_irq_ctrl, SYS_CLK_EN0_REG0, 14, CLK_IS_CRITICAL);
217 static C3_SYS_PCLK(sys_msr_clk, SYS_CLK_EN0_REG0, 15, 0);
218 static C3_SYS_PCLK(sys_rom, SYS_CLK_EN0_REG0, 16, 0);
219 static C3_SYS_PCLK(sys_uart_f, SYS_CLK_EN0_REG0, 17, 0);
220 static C3_SYS_PCLK(sys_cpu_apb, SYS_CLK_EN0_REG0, 18, 0);
221 static C3_SYS_PCLK(sys_rsa, SYS_CLK_EN0_REG0, 19, 0);
222 static C3_SYS_PCLK(sys_sar_adc, SYS_CLK_EN0_REG0, 20, 0);
223 static C3_SYS_PCLK(sys_startup, SYS_CLK_EN0_REG0, 21, 0);
224 static C3_SYS_PCLK(sys_secure, SYS_CLK_EN0_REG0, 22, 0);
225 static C3_SYS_PCLK(sys_spifc, SYS_CLK_EN0_REG0, 23, 0);
226 static C3_SYS_PCLK(sys_nna, SYS_CLK_EN0_REG0, 25, 0);
227 static C3_SYS_PCLK(sys_eth_mac, SYS_CLK_EN0_REG0, 26, 0);
235 static C3_SYS_PCLK(sys_gic, SYS_CLK_EN0_REG0, 27, CLK_IS_CRITICAL);
236 static C3_SYS_PCLK(sys_rama, SYS_CLK_EN0_REG0, 28, 0);
244 static C3_SYS_PCLK(sys_big_nic, SYS_CLK_EN0_REG0, 29, CLK_IS_CRITICAL);
245 static C3_SYS_PCLK(sys_ramb, SYS_CLK_EN0_REG0, 30, 0);
246 static C3_SYS_PCLK(sys_audio_pclk, SYS_CLK_EN0_REG0, 31, 0);
247 static C3_SYS_PCLK(sys_pwm_kl, SYS_CLK_EN0_REG1, 0, 0);
248 static C3_SYS_PCLK(sys_pwm_ij, SYS_CLK_EN0_REG1, 1, 0);
249 static C3_SYS_PCLK(sys_usb, SYS_CLK_EN0_REG1, 2, 0);
250 static C3_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG1, 3, 0);
251 static C3_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG1, 4, 0);
252 static C3_SYS_PCLK(sys_pwm_ab, SYS_CLK_EN0_REG1, 5, 0);
253 static C3_SYS_PCLK(sys_pwm_cd, SYS_CLK_EN0_REG1, 6, 0);
254 static C3_SYS_PCLK(sys_pwm_ef, SYS_CLK_EN0_REG1, 7, 0);
255 static C3_SYS_PCLK(sys_pwm_gh, SYS_CLK_EN0_REG1, 8, 0);
256 static C3_SYS_PCLK(sys_spicc_1, SYS_CLK_EN0_REG1, 9, 0);
257 static C3_SYS_PCLK(sys_spicc_0, SYS_CLK_EN0_REG1, 10, 0);
258 static C3_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 11, 0);
259 static C3_SYS_PCLK(sys_uart_b, SYS_CLK_EN0_REG1, 12, 0);
260 static C3_SYS_PCLK(sys_uart_c, SYS_CLK_EN0_REG1, 13, 0);
261 static C3_SYS_PCLK(sys_uart_d, SYS_CLK_EN0_REG1, 14, 0);
262 static C3_SYS_PCLK(sys_uart_e, SYS_CLK_EN0_REG1, 15, 0);
263 static C3_SYS_PCLK(sys_i2c_m_a, SYS_CLK_EN0_REG1, 16, 0);
264 static C3_SYS_PCLK(sys_i2c_m_b, SYS_CLK_EN0_REG1, 17, 0);
265 static C3_SYS_PCLK(sys_i2c_m_c, SYS_CLK_EN0_REG1, 18, 0);
266 static C3_SYS_PCLK(sys_i2c_m_d, SYS_CLK_EN0_REG1, 19, 0);
267 static C3_SYS_PCLK(sys_i2c_s_a, SYS_CLK_EN0_REG1, 20, 0);
268 static C3_SYS_PCLK(sys_rtc, SYS_CLK_EN0_REG1, 21, 0);
269 static C3_SYS_PCLK(sys_ge2d, SYS_CLK_EN0_REG1, 22, 0);
270 static C3_SYS_PCLK(sys_isp, SYS_CLK_EN0_REG1, 23, 0);
271 static C3_SYS_PCLK(sys_gpv_isp_nic, SYS_CLK_EN0_REG1, 24, 0);
272 static C3_SYS_PCLK(sys_gpv_cve_nic, SYS_CLK_EN0_REG1, 25, 0);
273 static C3_SYS_PCLK(sys_mipi_dsi_host, SYS_CLK_EN0_REG1, 26, 0);
274 static C3_SYS_PCLK(sys_mipi_dsi_phy, SYS_CLK_EN0_REG1, 27, 0);
275 static C3_SYS_PCLK(sys_eth_phy, SYS_CLK_EN0_REG1, 28, 0);
276 static C3_SYS_PCLK(sys_acodec, SYS_CLK_EN0_REG1, 29, 0);
277 static C3_SYS_PCLK(sys_dwap, SYS_CLK_EN0_REG1, 30, 0);
278 static C3_SYS_PCLK(sys_dos, SYS_CLK_EN0_REG1, 31, 0);
279 static C3_SYS_PCLK(sys_cve, SYS_CLK_EN0_REG2, 0, 0);
280 static C3_SYS_PCLK(sys_vout, SYS_CLK_EN0_REG2, 1, 0);
281 static C3_SYS_PCLK(sys_vc9000e, SYS_CLK_EN0_REG2, 2, 0);
282 static C3_SYS_PCLK(sys_pwm_mn, SYS_CLK_EN0_REG2, 3, 0);
283 static C3_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG2, 4, 0);
285 static const struct clk_parent_data c3_axi_pclk_parents = { .fw_name = "axiclk" };
294 static C3_AXI_PCLK(axi_sys_nic, AXI_CLK_EN0, 2, CLK_IS_CRITICAL);
295 static C3_AXI_PCLK(axi_isp_nic, AXI_CLK_EN0, 3, 0);
296 static C3_AXI_PCLK(axi_cve_nic, AXI_CLK_EN0, 4, 0);
297 static C3_AXI_PCLK(axi_ramb, AXI_CLK_EN0, 5, 0);
298 static C3_AXI_PCLK(axi_rama, AXI_CLK_EN0, 6, 0);
304 static C3_AXI_PCLK(axi_cpu_dmc, AXI_CLK_EN0, 7, CLK_IS_CRITICAL);
305 static C3_AXI_PCLK(axi_nic, AXI_CLK_EN0, 8, 0);
306 static C3_AXI_PCLK(axi_dma, AXI_CLK_EN0, 9, 0);
313 static C3_AXI_PCLK(axi_mux_nic, AXI_CLK_EN0, 10, 0);
314 static C3_AXI_PCLK(axi_cve, AXI_CLK_EN0, 12, 0);
320 static C3_AXI_PCLK(axi_dev1_dmc, AXI_CLK_EN0, 13, 0);
321 static C3_AXI_PCLK(axi_dev0_dmc, AXI_CLK_EN0, 14, 0);
322 static C3_AXI_PCLK(axi_dsp_dmc, AXI_CLK_EN0, 15, 0);
331 static struct clk_regmap c3_clk_12_24m_in = {
346 static struct clk_regmap c3_clk_12_24m = {
363 static struct clk_regmap c3_fclk_25m_div = {
379 static struct clk_regmap c3_fclk_25m = {
400 static u32 c3_gen_parents_val_table[] = { 0, 1, 2, 5, 6, 7, 17, 19, 20, 21, 22, 23, 24};
401 static const struct clk_parent_data c3_gen_parents[] = {
417 static struct clk_regmap c3_gen_sel = {
432 static struct clk_regmap c3_gen_div = {
449 static struct clk_regmap c3_gen = {
465 static const struct clk_parent_data c3_saradc_parents[] = {
470 static C3_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x1, c3_saradc_parents);
471 static C3_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8);
472 static C3_COMP_GATE(saradc, SAR_CLK_CTRL0, 8);
474 static const struct clk_parent_data c3_pwm_parents[] = {
481 static C3_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, c3_pwm_parents);
482 static C3_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8);
483 static C3_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8);
485 static C3_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, c3_pwm_parents);
486 static C3_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8);
487 static C3_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24);
489 static C3_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, c3_pwm_parents);
490 static C3_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8);
491 static C3_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8);
493 static C3_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, c3_pwm_parents);
494 static C3_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8);
495 static C3_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24);
497 static C3_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, c3_pwm_parents);
498 static C3_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8);
499 static C3_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8);
501 static C3_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, c3_pwm_parents);
502 static C3_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8);
503 static C3_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24);
505 static C3_COMP_SEL(pwm_g, PWM_CLK_GH_CTRL, 9, 0x3, c3_pwm_parents);
506 static C3_COMP_DIV(pwm_g, PWM_CLK_GH_CTRL, 0, 8);
507 static C3_COMP_GATE(pwm_g, PWM_CLK_GH_CTRL, 8);
509 static C3_COMP_SEL(pwm_h, PWM_CLK_GH_CTRL, 25, 0x3, c3_pwm_parents);
510 static C3_COMP_DIV(pwm_h, PWM_CLK_GH_CTRL, 16, 8);
511 static C3_COMP_GATE(pwm_h, PWM_CLK_GH_CTRL, 24);
513 static C3_COMP_SEL(pwm_i, PWM_CLK_IJ_CTRL, 9, 0x3, c3_pwm_parents);
514 static C3_COMP_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0, 8);
515 static C3_COMP_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8);
517 static C3_COMP_SEL(pwm_j, PWM_CLK_IJ_CTRL, 25, 0x3, c3_pwm_parents);
518 static C3_COMP_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16, 8);
519 static C3_COMP_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24);
521 static C3_COMP_SEL(pwm_k, PWM_CLK_KL_CTRL, 9, 0x3, c3_pwm_parents);
522 static C3_COMP_DIV(pwm_k, PWM_CLK_KL_CTRL, 0, 8);
523 static C3_COMP_GATE(pwm_k, PWM_CLK_KL_CTRL, 8);
525 static C3_COMP_SEL(pwm_l, PWM_CLK_KL_CTRL, 25, 0x3, c3_pwm_parents);
526 static C3_COMP_DIV(pwm_l, PWM_CLK_KL_CTRL, 16, 8);
527 static C3_COMP_GATE(pwm_l, PWM_CLK_KL_CTRL, 24);
529 static C3_COMP_SEL(pwm_m, PWM_CLK_MN_CTRL, 9, 0x3, c3_pwm_parents);
530 static C3_COMP_DIV(pwm_m, PWM_CLK_MN_CTRL, 0, 8);
531 static C3_COMP_GATE(pwm_m, PWM_CLK_MN_CTRL, 8);
533 static C3_COMP_SEL(pwm_n, PWM_CLK_MN_CTRL, 25, 0x3, c3_pwm_parents);
534 static C3_COMP_DIV(pwm_n, PWM_CLK_MN_CTRL, 16, 8);
535 static C3_COMP_GATE(pwm_n, PWM_CLK_MN_CTRL, 24);
537 static const struct clk_parent_data c3_spicc_parents[] = {
548 static C3_COMP_SEL(spicc_a, SPICC_CLK_CTRL, 7, 0x7, c3_spicc_parents);
549 static C3_COMP_DIV(spicc_a, SPICC_CLK_CTRL, 0, 6);
550 static C3_COMP_GATE(spicc_a, SPICC_CLK_CTRL, 6);
552 static C3_COMP_SEL(spicc_b, SPICC_CLK_CTRL, 23, 0x7, c3_spicc_parents);
553 static C3_COMP_DIV(spicc_b, SPICC_CLK_CTRL, 16, 6);
554 static C3_COMP_GATE(spicc_b, SPICC_CLK_CTRL, 22);
556 static const struct clk_parent_data c3_spifc_parents[] = {
567 static C3_COMP_SEL(spifc, SPIFC_CLK_CTRL, 9, 0x7, c3_spifc_parents);
568 static C3_COMP_DIV(spifc, SPIFC_CLK_CTRL, 0, 7);
569 static C3_COMP_GATE(spifc, SPIFC_CLK_CTRL, 8);
571 static const struct clk_parent_data c3_sd_emmc_parents[] = {
582 static C3_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, c3_sd_emmc_parents);
583 static C3_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7);
584 static C3_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7);
586 static C3_COMP_SEL(sd_emmc_b, SD_EMMC_CLK_CTRL, 25, 0x7, c3_sd_emmc_parents);
587 static C3_COMP_DIV(sd_emmc_b, SD_EMMC_CLK_CTRL, 16, 7);
588 static C3_COMP_GATE(sd_emmc_b, SD_EMMC_CLK_CTRL, 23);
590 static C3_COMP_SEL(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, c3_sd_emmc_parents);
591 static C3_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7);
592 static C3_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7);
594 static struct clk_regmap c3_ts_div = {
610 static struct clk_regmap c3_ts = {
626 static const struct clk_parent_data c3_eth_parents = {
630 static struct clk_fixed_factor c3_eth_125m_div = {
641 static struct clk_regmap c3_eth_125m = {
657 static struct clk_regmap c3_eth_rmii_div = {
671 static struct clk_regmap c3_eth_rmii = {
687 static const struct clk_parent_data c3_mipi_dsi_meas_parents[] = {
698 static C3_COMP_SEL(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 21, 0x7, c3_mipi_dsi_meas_parents);
699 static C3_COMP_DIV(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 12, 7);
700 static C3_COMP_GATE(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 20);
702 static const struct clk_parent_data c3_dsi_phy_parents[] = {
713 static C3_COMP_SEL(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 12, 0x7, c3_dsi_phy_parents);
714 static C3_COMP_DIV(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 0, 7);
715 static C3_COMP_GATE(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 8);
717 static const struct clk_parent_data c3_vout_mclk_parents[] = {
728 static C3_COMP_SEL(vout_mclk, VOUTENC_CLK_CTRL, 9, 0x7, c3_vout_mclk_parents);
729 static C3_COMP_DIV(vout_mclk, VOUTENC_CLK_CTRL, 0, 7);
730 static C3_COMP_GATE(vout_mclk, VOUTENC_CLK_CTRL, 8);
732 static const struct clk_parent_data c3_vout_enc_parents[] = {
743 static C3_COMP_SEL(vout_enc, VOUTENC_CLK_CTRL, 25, 0x7, c3_vout_enc_parents);
744 static C3_COMP_DIV(vout_enc, VOUTENC_CLK_CTRL, 16, 7);
745 static C3_COMP_GATE(vout_enc, VOUTENC_CLK_CTRL, 24);
747 static const struct clk_parent_data c3_hcodec_pre_parents[] = {
758 static C3_COMP_SEL(hcodec_0, VDEC_CLK_CTRL, 9, 0x7, c3_hcodec_pre_parents);
759 static C3_COMP_DIV(hcodec_0, VDEC_CLK_CTRL, 0, 7);
760 static C3_COMP_GATE(hcodec_0, VDEC_CLK_CTRL, 8);
762 static C3_COMP_SEL(hcodec_1, VDEC3_CLK_CTRL, 9, 0x7, c3_hcodec_pre_parents);
763 static C3_COMP_DIV(hcodec_1, VDEC3_CLK_CTRL, 0, 7);
764 static C3_COMP_GATE(hcodec_1, VDEC3_CLK_CTRL, 8);
766 static const struct clk_parent_data c3_hcodec_parents[] = {
771 static struct clk_regmap c3_hcodec = {
786 static const struct clk_parent_data c3_vc9000e_parents[] = {
797 static C3_COMP_SEL(vc9000e_aclk, VC9000E_CLK_CTRL, 9, 0x7, c3_vc9000e_parents);
798 static C3_COMP_DIV(vc9000e_aclk, VC9000E_CLK_CTRL, 0, 7);
799 static C3_COMP_GATE(vc9000e_aclk, VC9000E_CLK_CTRL, 8);
801 static C3_COMP_SEL(vc9000e_core, VC9000E_CLK_CTRL, 25, 0x7, c3_vc9000e_parents);
802 static C3_COMP_DIV(vc9000e_core, VC9000E_CLK_CTRL, 16, 7);
803 static C3_COMP_GATE(vc9000e_core, VC9000E_CLK_CTRL, 24);
805 static const struct clk_parent_data c3_csi_phy_parents[] = {
816 static C3_COMP_SEL(csi_phy0, ISP0_CLK_CTRL, 25, 0x7, c3_csi_phy_parents);
817 static C3_COMP_DIV(csi_phy0, ISP0_CLK_CTRL, 16, 7);
818 static C3_COMP_GATE(csi_phy0, ISP0_CLK_CTRL, 24);
820 static const struct clk_parent_data c3_dewarpa_parents[] = {
831 static C3_COMP_SEL(dewarpa, DEWARPA_CLK_CTRL, 9, 0x7, c3_dewarpa_parents);
832 static C3_COMP_DIV(dewarpa, DEWARPA_CLK_CTRL, 0, 7);
833 static C3_COMP_GATE(dewarpa, DEWARPA_CLK_CTRL, 8);
835 static const struct clk_parent_data c3_isp_parents[] = {
846 static C3_COMP_SEL(isp0, ISP0_CLK_CTRL, 9, 0x7, c3_isp_parents);
847 static C3_COMP_DIV(isp0, ISP0_CLK_CTRL, 0, 7);
848 static C3_COMP_GATE(isp0, ISP0_CLK_CTRL, 8);
850 static const struct clk_parent_data c3_nna_core_parents[] = {
861 static C3_COMP_SEL(nna_core, NNA_CLK_CTRL, 9, 0x7, c3_nna_core_parents);
862 static C3_COMP_DIV(nna_core, NNA_CLK_CTRL, 0, 7);
863 static C3_COMP_GATE(nna_core, NNA_CLK_CTRL, 8);
865 static const struct clk_parent_data c3_ge2d_parents[] = {
876 static C3_COMP_SEL(ge2d, GE2D_CLK_CTRL, 9, 0x7, c3_ge2d_parents);
877 static C3_COMP_DIV(ge2d, GE2D_CLK_CTRL, 0, 7);
878 static C3_COMP_GATE(ge2d, GE2D_CLK_CTRL, 8);
880 static const struct clk_parent_data c3_vapb_parents[] = {
891 static C3_COMP_SEL(vapb, VAPB_CLK_CTRL, 9, 0x7, c3_vapb_parents);
892 static C3_COMP_DIV(vapb, VAPB_CLK_CTRL, 0, 7);
893 static C3_COMP_GATE(vapb, VAPB_CLK_CTRL, 8);
895 static struct clk_hw *c3_peripherals_hw_clks[] = {
1099 static const struct meson_clkc_data c3_peripherals_clkc_data = {
1106 static const struct of_device_id c3_peripherals_clkc_match_table[] = {
1116 static struct platform_driver c3_peripherals_clkc_driver = {