Lines Matching +full:0 +full:x168
19 #define HHI_GP0_PLL_CNTL 0x40
20 #define HHI_GP0_PLL_CNTL2 0x44
21 #define HHI_GP0_PLL_CNTL3 0x48
22 #define HHI_GP0_PLL_CNTL4 0x4c
23 #define HHI_GP0_PLL_CNTL5 0x50
24 #define HHI_GP0_PLL_STS 0x54
25 #define HHI_GP0_PLL_CNTL1 0x58
26 #define HHI_HIFI_PLL_CNTL 0x80
27 #define HHI_HIFI_PLL_CNTL2 0x84
28 #define HHI_HIFI_PLL_CNTL3 0x88
29 #define HHI_HIFI_PLL_CNTL4 0x8C
30 #define HHI_HIFI_PLL_CNTL5 0x90
31 #define HHI_HIFI_PLL_STS 0x94
32 #define HHI_HIFI_PLL_CNTL1 0x98
34 #define HHI_XTAL_DIVN_CNTL 0xbc
35 #define HHI_GCLK2_MPEG0 0xc0
36 #define HHI_GCLK2_MPEG1 0xc4
37 #define HHI_GCLK2_MPEG2 0xc8
38 #define HHI_GCLK2_OTHER 0xd0
39 #define HHI_GCLK2_AO 0xd4
40 #define HHI_PCIE_PLL_CNTL 0xd8
41 #define HHI_PCIE_PLL_CNTL1 0xdC
42 #define HHI_PCIE_PLL_CNTL2 0xe0
43 #define HHI_PCIE_PLL_CNTL3 0xe4
44 #define HHI_PCIE_PLL_CNTL4 0xe8
45 #define HHI_PCIE_PLL_CNTL5 0xec
46 #define HHI_PCIE_PLL_CNTL6 0xf0
47 #define HHI_PCIE_PLL_STS 0xf4
49 #define HHI_MEM_PD_REG0 0x100
50 #define HHI_VPU_MEM_PD_REG0 0x104
51 #define HHI_VIID_CLK_DIV 0x128
52 #define HHI_VIID_CLK_CNTL 0x12c
54 #define HHI_GCLK_MPEG0 0x140
55 #define HHI_GCLK_MPEG1 0x144
56 #define HHI_GCLK_MPEG2 0x148
57 #define HHI_GCLK_OTHER 0x150
58 #define HHI_GCLK_AO 0x154
59 #define HHI_SYS_CPU_CLK_CNTL1 0x15c
60 #define HHI_SYS_CPU_RESET_CNTL 0x160
61 #define HHI_VID_CLK_DIV 0x164
62 #define HHI_SPICC_HCLK_CNTL 0x168
64 #define HHI_MPEG_CLK_CNTL 0x174
65 #define HHI_VID_CLK_CNTL 0x17c
66 #define HHI_TS_CLK_CNTL 0x190
67 #define HHI_VID_CLK_CNTL2 0x194
68 #define HHI_SYS_CPU_CLK_CNTL0 0x19c
69 #define HHI_VID_PLL_CLK_DIV 0x1a0
70 #define HHI_VPU_CLK_CNTL 0x1bC
72 #define HHI_VAPBCLK_CNTL 0x1F4
74 #define HHI_GEN_CLK_CNTL 0x228
76 #define HHI_VDIN_MEAS_CLK_CNTL 0x250
77 #define HHI_NAND_CLK_CNTL 0x25C
78 #define HHI_SD_EMMC_CLK_CNTL 0x264
80 #define HHI_MPLL_CNTL 0x280
81 #define HHI_MPLL_CNTL2 0x284
82 #define HHI_MPLL_CNTL3 0x288
83 #define HHI_MPLL_CNTL4 0x28C
84 #define HHI_MPLL_CNTL5 0x290
85 #define HHI_MPLL_CNTL6 0x294
86 #define HHI_MPLL_CNTL7 0x298
87 #define HHI_MPLL_CNTL8 0x29C
88 #define HHI_MPLL_CNTL9 0x2A0
89 #define HHI_MPLL_CNTL10 0x2A4
91 #define HHI_MPLL3_CNTL0 0x2E0
92 #define HHI_MPLL3_CNTL1 0x2E4
93 #define HHI_PLL_TOP_MISC 0x2E8
95 #define HHI_SYS_PLL_CNTL1 0x2FC
96 #define HHI_SYS_PLL_CNTL 0x300
97 #define HHI_SYS_PLL_CNTL2 0x304
98 #define HHI_SYS_PLL_CNTL3 0x308
99 #define HHI_SYS_PLL_CNTL4 0x30c
100 #define HHI_SYS_PLL_CNTL5 0x310
101 #define HHI_SYS_PLL_STS 0x314
102 #define HHI_DPLL_TOP_I 0x318
103 #define HHI_DPLL_TOP2_I 0x31C