Lines Matching +full:data +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
18 #include "clk-regmap.h"
19 #include "clk-pll.h"
20 #include "clk-mpll.h"
22 #include "meson-eeclk.h"
24 #include <dt-bindings/clock/axg-clkc.h>
27 .data = &(struct meson_clk_pll_data){
31 .width = 1,
36 .width = 9,
41 .width = 5,
46 .width = 12,
51 .width = 1,
56 .width = 1,
70 .data = &(struct clk_regmap_div_data){
73 .width = 2,
91 .data = &(struct meson_clk_pll_data){
95 .width = 1,
100 .width = 9,
105 .width = 5,
110 .width = 1,
115 .width = 1,
129 .data = &(struct clk_regmap_div_data){
132 .width = 2,
188 .data = &(struct meson_clk_pll_data){
192 .width = 1,
197 .width = 9,
202 .width = 5,
207 .width = 10,
212 .width = 1,
217 .width = 1,
234 .data = &(struct clk_regmap_div_data){
237 .width = 2,
260 .data = &(struct meson_clk_pll_data){
264 .width = 1,
269 .width = 9,
274 .width = 5,
279 .width = 13,
284 .width = 1,
289 .width = 1,
307 .data = &(struct clk_regmap_div_data){
310 .width = 2,
336 .data = &(struct clk_regmap_gate_data){
363 .data = &(struct clk_regmap_gate_data){
382 * b) CCF has a clock hand-off mechanism to make the sure the
401 .data = &(struct clk_regmap_gate_data){
427 .data = &(struct clk_regmap_gate_data){
455 .data = &(struct clk_regmap_gate_data){
470 .data = &(struct clk_regmap_div_data){
473 .width = 1,
486 .data = &(struct meson_clk_mpll_data){
490 .width = 14,
495 .width = 1,
500 .width = 9,
505 .width = 1,
520 .data = &(struct clk_regmap_gate_data){
536 .data = &(struct meson_clk_mpll_data){
540 .width = 14,
545 .width = 1,
550 .width = 9,
555 .width = 1,
570 .data = &(struct clk_regmap_gate_data){
586 .data = &(struct meson_clk_mpll_data){
590 .width = 14,
595 .width = 1,
600 .width = 9,
605 .width = 1,
610 .width = 1,
625 .data = &(struct clk_regmap_gate_data){
641 .data = &(struct meson_clk_mpll_data){
645 .width = 14,
650 .width = 1,
655 .width = 9,
660 .width = 1,
675 .data = &(struct clk_regmap_gate_data){
709 .data = &(struct meson_clk_pll_data){
713 .width = 1,
718 .width = 9,
723 .width = 5,
728 .width = 12,
733 .width = 1,
738 .width = 1,
755 .data = &(struct clk_regmap_div_data){
758 .width = 2,
773 .data = &(struct clk_regmap_div_data){
776 .width = 2,
791 .data = &(struct clk_regmap_mux_data){
808 .data = &(struct clk_regmap_mux_data){
825 .data = &(struct clk_regmap_gate_data){
840 .data = &(struct clk_regmap_gate_data){
865 .data = &(struct clk_regmap_mux_data){
880 .data = &(struct clk_regmap_div_data){
883 .width = 7,
897 .data = &(struct clk_regmap_gate_data){
928 .data = &(struct clk_regmap_mux_data){
943 .data = &(struct clk_regmap_div_data){
946 .width = 7,
961 .data = &(struct clk_regmap_gate_data){
978 .data = &(struct clk_regmap_mux_data){
993 .data = &(struct clk_regmap_div_data){
996 .width = 7,
1011 .data = &(struct clk_regmap_gate_data){
1036 .data = &(struct clk_regmap_mux_data){
1052 .data = &(struct clk_regmap_div_data){
1055 .width = 7,
1067 .data = &(struct clk_regmap_gate_data){
1085 .data = &(struct clk_regmap_mux_data){
1101 .data = &(struct clk_regmap_div_data){
1104 .width = 7,
1116 .data = &(struct clk_regmap_gate_data){
1134 .data = &(struct clk_regmap_mux_data){
1154 .data = &(struct clk_regmap_mux_data){
1169 .data = &(struct clk_regmap_div_data){
1172 .width = 7,
1186 .data = &(struct clk_regmap_gate_data){
1202 .data = &(struct clk_regmap_mux_data){
1217 .data = &(struct clk_regmap_div_data){
1220 .width = 7,
1234 .data = &(struct clk_regmap_gate_data){
1250 .data = &(struct clk_regmap_mux_data){
1268 .data = &(struct clk_regmap_gate_data){
1294 .data = &(struct clk_regmap_mux_data){
1309 .data = &(struct clk_regmap_mux_data){
1324 .data = &(struct clk_regmap_gate_data){
1338 .data = &(struct clk_regmap_gate_data){
1352 .data = &(struct clk_regmap_div_data){
1355 .width = 8,
1369 .data = &(struct clk_regmap_div_data){
1372 .width = 8,
1386 .data = &(struct clk_regmap_gate_data){
1400 .data = &(struct clk_regmap_gate_data){
1414 .data = &(struct clk_regmap_gate_data){
1428 .data = &(struct clk_regmap_gate_data){
1442 .data = &(struct clk_regmap_gate_data){
1456 .data = &(struct clk_regmap_gate_data){
1470 .data = &(struct clk_regmap_gate_data){
1484 .data = &(struct clk_regmap_gate_data){
1498 .data = &(struct clk_regmap_gate_data){
1512 .data = &(struct clk_regmap_gate_data){
1526 .data = &(struct clk_regmap_gate_data){
1540 .data = &(struct clk_regmap_gate_data){
1672 .data = &(struct clk_regmap_mux_data){
1688 .data = &(struct clk_regmap_gate_data){
1716 .data = &(struct clk_regmap_mux_data){
1733 .data = &(struct clk_regmap_div_data){
1736 .width = 7,
1749 .data = &(struct clk_regmap_gate_data){
1780 .data = &(struct clk_regmap_mux_data){
1801 .data = &(struct clk_regmap_div_data){
1804 .width = 11,
1818 .data = &(struct clk_regmap_gate_data){
2168 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
2176 .name = "axg-clkc",