Lines Matching defs:_name
80 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \
86 .name = "aud_"#_name, \
94 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \
102 .name = "aud_"#_name, \
110 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \
118 .name = "aud_"#_name, \
126 #define AUD_PCLK_GATE(_name, _reg, _bit) { \
132 .name = "aud_"#_name, \
139 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \
154 .name = "aud_"#_name, \
162 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
182 .name = "aud_"#_name, \
190 #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \
199 .name = "aud_"#_name, \
207 #define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \
222 .name = "aud_"#_name, \
242 #define AUD_MST_MUX(_name, _reg, _flag) \
243 AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
245 #define AUD_MST_DIV(_name, _reg, _flag) \
246 AUD_DIV(_name##_div, _reg, 0, 16, _flag, \
247 aud_##_name##_sel, CLK_SET_RATE_PARENT)
248 #define AUD_MST_MCLK_GATE(_name, _reg) \
249 AUD_GATE(_name, _reg, 31, aud_##_name##_div, \
252 #define AUD_MST_MCLK_MUX(_name, _reg) \
253 AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
254 #define AUD_MST_MCLK_DIV(_name, _reg) \
255 AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
257 #define AUD_MST_SYS_MUX(_name, _reg) \
258 AUD_MST_MUX(_name, _reg, 0)
259 #define AUD_MST_SYS_DIV(_name, _reg) \
260 AUD_MST_DIV(_name, _reg, 0)
263 #define AUD_MST_SCLK_PRE_EN(_name, _reg) \
264 AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \
265 aud_mst_##_name##_mclk, 0)
266 #define AUD_MST_SCLK_DIV(_name, _reg) \
267 AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \
268 aud_mst_##_name##_sclk_pre_en, \
270 #define AUD_MST_SCLK_POST_EN(_name, _reg) \
271 AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \
272 aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
273 #define AUD_MST_SCLK(_name, _reg) \
274 AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \
275 aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
277 #define AUD_MST_LRCLK_DIV(_name, _reg) \
278 AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \
279 aud_mst_##_name##_sclk_post_en, 0)
280 #define AUD_MST_LRCLK(_name, _reg) \
281 AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \
282 aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
324 #define AUD_TDM_SCLK_MUX(_name, _reg) \
325 AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \
327 #define AUD_TDM_SCLK_PRE_EN(_name, _reg) \
328 AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \
329 aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
330 #define AUD_TDM_SCLK_POST_EN(_name, _reg) \
331 AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \
332 aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
333 #define AUD_TDM_SCLK(_name, _reg) \
334 AUD_PHASE(tdm##_name##_sclk, _reg, 1, 29, \
335 aud_tdm##_name##_sclk_post_en, \
337 #define AUD_TDM_SCLK_WS(_name, _reg) \
338 AUD_SCLK_WS(tdm##_name##_sclk, _reg, 1, 29, 28, \
339 aud_tdm##_name##_sclk_post_en, \
342 #define AUD_TDM_LRLCK(_name, _reg) \
343 AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
376 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \
377 AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents, \