1 // SPDX-License-Identifier: GPL-2.0-only
4  * Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
14 #include "clk-mtk.h"
15 #include "clk-pllfh.h"
16 #include "clk-fhctl.h"
37 	return fh->ops->hopping(fh, pcw, postdiv);  in mtk_fhctl_set_rate()
94 					   "mediatek,hopping-ssc-percent",  in fhctl_parse_dt()
101 		pllfh->state.fh_enable = 1;  in fhctl_parse_dt()
102 		pllfh->state.ssc_rate = ssc_rate;  in fhctl_parse_dt()
103 		pllfh->state.base = base;  in fhctl_parse_dt()
117 	struct fh_pll_regs *regs = &fh->regs;  in pllfh_init()
119 	void __iomem *base = pllfh_data->state.base;  in pllfh_init()
120 	void __iomem *fhx_base = base + pllfh_data->data.fhx_offset;  in pllfh_init()
122 	offset = fhctl_get_offset_table(pllfh_data->data.fh_ver);  in pllfh_init()
126 	regs->reg_hp_en = base + offset->offset_hp_en;  in pllfh_init()
127 	regs->reg_clk_con = base + offset->offset_clk_con;  in pllfh_init()
128 	regs->reg_rst_con = base + offset->offset_rst_con;  in pllfh_init()
129 	regs->reg_slope0 = base + offset->offset_slope0;  in pllfh_init()
130 	regs->reg_slope1 = base + offset->offset_slope1;  in pllfh_init()
132 	regs->reg_cfg = fhx_base + offset->offset_cfg;  in pllfh_init()
133 	regs->reg_updnlmt = fhx_base + offset->offset_updnlmt;  in pllfh_init()
134 	regs->reg_dds = fhx_base + offset->offset_dds;  in pllfh_init()
135 	regs->reg_dvfs = fhx_base + offset->offset_dvfs;  in pllfh_init()
136 	regs->reg_mon = fhx_base + offset->offset_mon;  in pllfh_init()
138 	fh->pllfh_data = pllfh_data;  in pllfh_init()
139 	fh->lock = &pllfh_lock;  in pllfh_init()
141 	fh->ops = fhctl_get_ops();  in pllfh_init()
148 	return pllfh && (pllfh->state.fh_enable == 1);  in fhctl_is_supported_and_enabled()
161 		return ERR_PTR(-ENOMEM);  in mtk_clk_register_pllfh()
169 	hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base,  in mtk_clk_register_pllfh()
209 		return -EINVAL;  in mtk_clk_register_pllfhs()
217 		pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);  in mtk_clk_register_pllfhs()
227 			       use_fhctl ? "fhpll" : "pll", pll->name,  in mtk_clk_register_pllfhs()
232 		clk_data->hws[pll->id] = hw;  in mtk_clk_register_pllfhs()
238 	while (--i >= 0) {  in mtk_clk_register_pllfhs()
243 		pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);  in mtk_clk_register_pllfhs()
247 			mtk_clk_unregister_pllfh(clk_data->hws[pll->id]);  in mtk_clk_register_pllfhs()
249 			mtk_clk_unregister_pll(clk_data->hws[pll->id]);  in mtk_clk_register_pllfhs()
251 		clk_data->hws[pll->id] = ERR_PTR(-ENOENT);  in mtk_clk_register_pllfhs()
270 	for (i = num_plls; i > 0; i--) {  in mtk_clk_unregister_pllfhs()
271 		const struct mtk_pll_data *pll = &plls[i - 1];  in mtk_clk_unregister_pllfhs()
275 		if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))  in mtk_clk_unregister_pllfhs()
278 		pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);  in mtk_clk_unregister_pllfhs()
282 			fhctl_base = pllfh->state.base;  in mtk_clk_unregister_pllfhs()
283 			mtk_clk_unregister_pllfh(clk_data->hws[pll->id]);  in mtk_clk_unregister_pllfhs()
285 			base = mtk_clk_pll_get_base(clk_data->hws[pll->id],  in mtk_clk_unregister_pllfhs()
287 			mtk_clk_unregister_pll(clk_data->hws[pll->id]);  in mtk_clk_unregister_pllfhs()
290 		clk_data->hws[pll->id] = ERR_PTR(-ENOENT);  in mtk_clk_unregister_pllfhs()