20 #include "clk-mux.h"
40 	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);  in mtk_clk_mux_fenc_enable_setclr()  local
45 	if (mux->lock)  in mtk_clk_mux_fenc_enable_setclr()
46 		spin_lock_irqsave(mux->lock, flags);  in mtk_clk_mux_fenc_enable_setclr()
48 		__acquire(mux->lock);  in mtk_clk_mux_fenc_enable_setclr()
50 	regmap_write(mux->regmap, mux->data->clr_ofs,  in mtk_clk_mux_fenc_enable_setclr()
51 		     BIT(mux->data->gate_shift));  in mtk_clk_mux_fenc_enable_setclr()
53 	ret = regmap_read_poll_timeout_atomic(mux->regmap, mux->data->fenc_sta_mon_ofs,  in mtk_clk_mux_fenc_enable_setclr()
54 					      val, val & BIT(mux->data->fenc_shift), 1,  in mtk_clk_mux_fenc_enable_setclr()
57 	if (mux->lock)  in mtk_clk_mux_fenc_enable_setclr()
58 		spin_unlock_irqrestore(mux->lock, flags);  in mtk_clk_mux_fenc_enable_setclr()
60 		__release(mux->lock);  in mtk_clk_mux_fenc_enable_setclr()
67 	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);  in mtk_clk_mux_enable_setclr()  local
70 	if (mux->lock)  in mtk_clk_mux_enable_setclr()
71 		spin_lock_irqsave(mux->lock, flags);  in mtk_clk_mux_enable_setclr()
73 		__acquire(mux->lock);  in mtk_clk_mux_enable_setclr()
75 	regmap_write(mux->regmap, mux->data->clr_ofs,  in mtk_clk_mux_enable_setclr()
76 		     BIT(mux->data->gate_shift));  in mtk_clk_mux_enable_setclr()
80 	 * not be effective yet. Set the update bit to ensure the mux gets  in mtk_clk_mux_enable_setclr()
83 	if (mux->reparent && mux->data->upd_shift >= 0) {  in mtk_clk_mux_enable_setclr()
84 		regmap_write(mux->regmap, mux->data->upd_ofs,  in mtk_clk_mux_enable_setclr()
85 			     BIT(mux->data->upd_shift));  in mtk_clk_mux_enable_setclr()
86 		mux->reparent = false;  in mtk_clk_mux_enable_setclr()
89 	if (mux->lock)  in mtk_clk_mux_enable_setclr()
90 		spin_unlock_irqrestore(mux->lock, flags);  in mtk_clk_mux_enable_setclr()
92 		__release(mux->lock);  in mtk_clk_mux_enable_setclr()
99 	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);  in mtk_clk_mux_disable_setclr()  local
101 	regmap_write(mux->regmap, mux->data->set_ofs,  in mtk_clk_mux_disable_setclr()
102 			BIT(mux->data->gate_shift));  in mtk_clk_mux_disable_setclr()
107 	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);  in mtk_clk_mux_fenc_is_enabled()  local
110 	regmap_read(mux->regmap, mux->data->fenc_sta_mon_ofs, &val);  in mtk_clk_mux_fenc_is_enabled()
112 	return !!(val & BIT(mux->data->fenc_shift));  in mtk_clk_mux_fenc_is_enabled()
117 	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);  in mtk_clk_mux_is_enabled()  local
120 	regmap_read(mux->regmap, mux->data->mux_ofs, &val);  in mtk_clk_mux_is_enabled()
122 	return (val & BIT(mux->data->gate_shift)) == 0;  in mtk_clk_mux_is_enabled()
127 	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);  in mtk_clk_mux_hwv_fenc_enable()  local
131 	regmap_write(mux->regmap_hwv, mux->data->hwv_set_ofs,  in mtk_clk_mux_hwv_fenc_enable()
132 		     BIT(mux->data->gate_shift));  in mtk_clk_mux_hwv_fenc_enable()
134 	ret = regmap_read_poll_timeout_atomic(mux->regmap_hwv, mux->data->hwv_sta_ofs,  in mtk_clk_mux_hwv_fenc_enable()
135 					      val, val & BIT(mux->data->gate_shift), 0,  in mtk_clk_mux_hwv_fenc_enable()
140 	ret = regmap_read_poll_timeout_atomic(mux->regmap, mux->data->fenc_sta_mon_ofs,  in mtk_clk_mux_hwv_fenc_enable()
141 					      val, val & BIT(mux->data->fenc_shift), 1,  in mtk_clk_mux_hwv_fenc_enable()
149 	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);  in mtk_clk_mux_hwv_disable()  local
152 	regmap_write(mux->regmap_hwv, mux->data->hwv_clr_ofs,  in mtk_clk_mux_hwv_disable()
153 		     BIT(mux->data->gate_shift));  in mtk_clk_mux_hwv_disable()
155 	regmap_read_poll_timeout_atomic(mux->regmap_hwv, mux->data->hwv_sta_ofs,  in mtk_clk_mux_hwv_disable()
156 					val, (val & BIT(mux->data->gate_shift)),  in mtk_clk_mux_hwv_disable()
162 	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);  in mtk_clk_mux_get_parent()  local
163 	u32 mask = GENMASK(mux->data->mux_width - 1, 0);  in mtk_clk_mux_get_parent()
166 	regmap_read(mux->regmap, mux->data->mux_ofs, &val);  in mtk_clk_mux_get_parent()
167 	val = (val >> mux->data->mux_shift) & mask;  in mtk_clk_mux_get_parent()
169 	if (mux->data->parent_index) {  in mtk_clk_mux_get_parent()
172 		for (i = 0; i < mux->data->num_parents; i++)  in mtk_clk_mux_get_parent()
173 			if (mux->data->parent_index[i] == val)  in mtk_clk_mux_get_parent()
177 		return mux->data->num_parents + 1;  in mtk_clk_mux_get_parent()
185 	struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);  in mtk_clk_mux_set_parent_setclr_lock()  local
186 	u32 mask = GENMASK(mux->data->mux_width - 1, 0);  in mtk_clk_mux_set_parent_setclr_lock()
190 	if (mux->lock)  in mtk_clk_mux_set_parent_setclr_lock()
191 		spin_lock_irqsave(mux->lock, flags);  in mtk_clk_mux_set_parent_setclr_lock()
193 		__acquire(mux->lock);  in mtk_clk_mux_set_parent_setclr_lock()
195 	if (mux->data->parent_index)  in mtk_clk_mux_set_parent_setclr_lock()
196 		index = mux->data->parent_index[index];  in mtk_clk_mux_set_parent_setclr_lock()
198 	regmap_read(mux->regmap, mux->data->mux_ofs, &orig);  in mtk_clk_mux_set_parent_setclr_lock()
199 	val = (orig & ~(mask << mux->data->mux_shift))  in mtk_clk_mux_set_parent_setclr_lock()
200 			| (index << mux->data->mux_shift);  in mtk_clk_mux_set_parent_setclr_lock()
203 		regmap_write(mux->regmap, mux->data->clr_ofs,  in mtk_clk_mux_set_parent_setclr_lock()
204 				mask << mux->data->mux_shift);  in mtk_clk_mux_set_parent_setclr_lock()
205 		regmap_write(mux->regmap, mux->data->set_ofs,  in mtk_clk_mux_set_parent_setclr_lock()
206 				index << mux->data->mux_shift);  in mtk_clk_mux_set_parent_setclr_lock()
208 		if (mux->data->upd_shift >= 0) {  in mtk_clk_mux_set_parent_setclr_lock()
209 			regmap_write(mux->regmap, mux->data->upd_ofs,  in mtk_clk_mux_set_parent_setclr_lock()
210 					BIT(mux->data->upd_shift));  in mtk_clk_mux_set_parent_setclr_lock()
211 			mux->reparent = true;  in mtk_clk_mux_set_parent_setclr_lock()
215 	if (mux->lock)  in mtk_clk_mux_set_parent_setclr_lock()
216 		spin_unlock_irqrestore(mux->lock, flags);  in mtk_clk_mux_set_parent_setclr_lock()
218 		__release(mux->lock);  in mtk_clk_mux_set_parent_setclr_lock()
275 					   const struct mtk_mux *mux,  in mtk_clk_register_mux()  argument
288 	init.name = mux->name;  in mtk_clk_register_mux()
289 	init.flags = mux->flags;  in mtk_clk_register_mux()
290 	init.parent_names = mux->parent_names;  in mtk_clk_register_mux()
291 	init.num_parents = mux->num_parents;  in mtk_clk_register_mux()
292 	init.ops = mux->ops;  in mtk_clk_register_mux()
300 	clk_mux->data = mux;  in mtk_clk_register_mux()
315 	struct mtk_clk_mux *mux;  in mtk_clk_unregister_mux()  local
319 	mux = to_mtk_clk_mux(hw);  in mtk_clk_unregister_mux()
322 	kfree(mux);  in mtk_clk_unregister_mux()
349 		const struct mtk_mux *mux = &muxes[i];  in mtk_clk_register_muxes()  local
351 		if (!IS_ERR_OR_NULL(clk_data->hws[mux->id])) {  in mtk_clk_register_muxes()
353 				node, mux->id);  in mtk_clk_register_muxes()
357 		hw = mtk_clk_register_mux(dev, mux, regmap, regmap_hwv, lock);  in mtk_clk_register_muxes()
360 			pr_err("Failed to register clk %s: %pe\n", mux->name,  in mtk_clk_register_muxes()
365 		clk_data->hws[mux->id] = hw;  in mtk_clk_register_muxes()
372 		const struct mtk_mux *mux = &muxes[i];  in mtk_clk_register_muxes()  local
374 		if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))  in mtk_clk_register_muxes()
377 		mtk_clk_unregister_mux(clk_data->hws[mux->id]);  in mtk_clk_register_muxes()
378 		clk_data->hws[mux->id] = ERR_PTR(-ENOENT);  in mtk_clk_register_muxes()
394 		const struct mtk_mux *mux = &muxes[i - 1];  in mtk_clk_unregister_muxes()  local
396 		if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))  in mtk_clk_unregister_muxes()
399 		mtk_clk_unregister_mux(clk_data->hws[mux->id]);  in mtk_clk_unregister_muxes()
400 		clk_data->hws[mux->id] = ERR_PTR(-ENOENT);  in mtk_clk_unregister_muxes()