Lines Matching +full:0 +full:x080

24 	FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
366 		0x000, 0, 1),
368 		0x000, 4, 4),
370 		0x000, 11, 3),
372 		0x000, 19, 1),
374 		0x000, 20, 3),
376 		0x000, 24, 2),
378 		0x000, 26, 1),
380 		0x000, 27, 3),
383 		0x004, 0, 7),
385 		0x004, 7, 1),
387 		0x004, 20, 3),
390 		0x040, 0, 3),
392 		0x040, 3, 3),
394 		0x040, 6, 3),
396 		0x040, 22, 1),
398 		0x040, 23, 1),
400 		0x040, 24, 2),
402 		0x040, 26, 2),
404 		0x040, 28, 2),
407 		0x044, 12, 1),
409 		0x044, 13, 1),
411 		0x044, 14, 1),
413 		0x044, 15, 1),
415 		0x044, 16, 1),
417 		0x044, 17, 1),
419 		0x044, 18, 1),
422 		0x07c, 0, 1),
424 		0x07c, 1, 2),
426 		0x07c, 3, 1),
428 		0x07c, 4, 1),
430 		0x07c, 5, 2),
432 		0x07c, 7, 3),
434 		0x07c, 10, 3),
436 		0x07c, 13, 3),
457 	MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
459 	MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
460 		0, 1),
461 	MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
463 	MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
465 	MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,
480 		0x0048, 0, 8),
482 		0x0048, 8, 8),
484 		0x0048, 16, 8),
486 		0x0048, 24, 8),
488 		0x004c, 0, 8),
490 		0x004c, 8, 8),
492 		0x004c, 16, 8),
494 		0x004c, 24, 8),
496 		0x0078, 0, 8),
500 	.set_ofs = 0x54,
501 	.clr_ofs = 0x84,
502 	.sta_ofs = 0x24,
506 	.set_ofs = 0x6c,
507 	.clr_ofs = 0x9c,
508 	.sta_ofs = 0x3c,
512 	.set_ofs = 0xa0,
513 	.clr_ofs = 0xb0,
514 	.sta_ofs = 0x70,
518 	.set_ofs = 0xa4,
519 	.clr_ofs = 0xb4,
520 	.sta_ofs = 0x74,
524 	.set_ofs = 0x44,
525 	.clr_ofs = 0x44,
526 	.sta_ofs = 0x44,
580 	GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
609 	GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
632 	GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),