Lines Matching +full:0 +full:x008
20 #define ARMPLL_LL_CON0 0x008
21 #define ARMPLL_LL_CON1 0x00c
22 #define ARMPLL_LL_CON2 0x010
23 #define ARMPLL_LL_CON3 0x014
24 #define ARMPLL_BL_CON0 0x008
25 #define ARMPLL_BL_CON1 0x00c
26 #define ARMPLL_BL_CON2 0x010
27 #define ARMPLL_BL_CON3 0x014
28 #define ARMPLL_B_CON0 0x008
29 #define ARMPLL_B_CON1 0x00c
30 #define ARMPLL_B_CON2 0x010
31 #define ARMPLL_B_CON3 0x014
32 #define CCIPLL_CON0 0x008
33 #define CCIPLL_CON1 0x00c
34 #define CCIPLL_CON2 0x010
35 #define CCIPLL_CON3 0x014
36 #define PTPPLL_CON0 0x008
37 #define PTPPLL_CON1 0x00c
38 #define PTPPLL_CON2 0x010
39 #define PTPPLL_CON3 0x014
72 PLL(CLK_CPBL_ARMPLL_BL, "armpll-bl", ARMPLL_BL_CON0, ARMPLL_BL_CON0, 0,
73 0, PLL_AO, BIT(0), ARMPLL_BL_CON1, 24, 0, 0, 0, ARMPLL_BL_CON1, 0, 22),
77 PLL(CLK_CPB_ARMPLL_B, "armpll-b", ARMPLL_B_CON0, ARMPLL_B_CON0, 0, 0,
78 PLL_AO, BIT(0), ARMPLL_B_CON1, 24, 0, 0, 0, ARMPLL_B_CON1, 0, 22),
82 PLL(CLK_CPLL_ARMPLL_LL, "armpll-ll", ARMPLL_LL_CON0, ARMPLL_LL_CON0, 0,
83 0, PLL_AO, BIT(0), ARMPLL_LL_CON1, 24, 0, 0, 0, ARMPLL_LL_CON1, 0, 22),
87 PLL(CLK_CCIPLL, "ccipll", CCIPLL_CON0, CCIPLL_CON0, 0, 0, PLL_AO,
88 BIT(0), CCIPLL_CON1, 24, 0, 0, 0, CCIPLL_CON1, 0, 22),
92 PLL(CLK_PTPPLL, "ptppll", PTPPLL_CON0, PTPPLL_CON0, 0, 0, PLL_AO,
93 BIT(0), PTPPLL_CON1, 24, 0, 0, 0, PTPPLL_CON1, 0, 22),