Lines Matching refs:MUX
524 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
526 MUX(CLK_TOP_GFMUX_EMI1X_SEL, "gfmux_emi1x_sel", gfmux_emi1x_parents,
528 MUX(CLK_TOP_EMI_DDRPHY_SEL, "emi_ddrphy_sel", emi_ddrphy_parents,
530 MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
532 MUX(CLK_TOP_CSW_MUX_MFG_SEL, "csw_mux_mfg_sel", csw_mux_mfg_parents,
534 MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
536 MUX(CLK_TOP_CAMTG_MM_SEL, "camtg_mm_sel", camtg_mm_parents,
538 MUX(CLK_TOP_PWM_MM_SEL, "pwm_mm_sel", pwm_mm_parents,
540 MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
542 MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
544 MUX(CLK_TOP_SPM_52M_SEL, "spm_52m_sel", spm_52m_parents,
546 MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
548 MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
550 MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
553 MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
555 MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
557 MUX(CLK_TOP_MFG_MM_SEL, "mfg_mm_sel", mfg_mm_parents,
559 MUX(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
561 MUX(CLK_TOP_SMI_MM_SEL, "smi_mm_sel", smi_mm_parents,
563 MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents,
565 MUX(CLK_TOP_SCAM_MM_SEL, "scam_mm_sel", scam_mm_parents,
568 MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents,
570 MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents,
572 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
574 MUX(CLK_TOP_VDEC_MM_SEL, "vdec_mm_sel", vdec_mm_parents,
576 MUX(CLK_TOP_DPI0_MM_SEL, "dpi0_mm_sel", dpi0_mm_parents,
578 MUX(CLK_TOP_DPI1_MM_SEL, "dpi1_mm_sel", dpi1_mm_parents,
580 MUX(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents,
582 MUX(CLK_TOP_SLOW_MFG_SEL, "slow_mfg_sel", slow_mfg_parents,
584 MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
586 MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
588 MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
590 MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
592 MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
595 MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents,
597 MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents,
599 MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents,
601 MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents,
603 MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents,
605 MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents,
607 MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents,
610 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
612 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
614 MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents,
616 MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents,
618 MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents,
620 MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents,
622 MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents,
624 MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
646 MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
648 MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
650 MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
652 MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
654 MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,