Lines Matching +full:0 +full:x25c

15 #define REG_REF2USB		0x8
16 #define REG_AP_PLL_CON7		0x1c
17  #define MD1_MTCMOS_OFF		BIT(0)
23 #define MT6795_CON0_EN		BIT(0)
43 		.pll_en_bit = 0,					\
47 	PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO,
48 	    21, 0x204, 24, 0x0, 0x204, 0),
49 	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,
50 	    21, 0x220, 4, 0x0, 0x224, 0),
51 	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR,
52 	    7, 0x230, 4, 0x0, 0x234, 14),
53 	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0),
54 	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
55 	PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
56 	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
57 	PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
58 	PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4, 0x0, 0x294, 0),
59 	PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a8, 0x2a4, 0),
60 	PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2bc, 0x2b8, 0),
82 			.dds_mask = GENMASK(21, 0),			\
87 			.fhctlx_en = BIT(0),				\
91 			.dt_val = 0x0,					\
92 			.df_val = 0x9,					\
99 #define FH(_pllid, _fhid, _offset)	_FH(_pllid, _fhid, 0x6003c97, _offset)
100 #define FH_M(_pllid, _fhid, _offset)	_FH(_pllid, _fhid, 0x6000140, _offset)
103 	FH(CLK_APMIXED_ARMCA53PLL, FH_CA53PLL_BL, 0x38),
104 	FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60),
105 	FH_M(CLK_APMIXED_MPLL, FH_MPLL, 0x74),
106 	FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88),
107 	FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c),
108 	FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0),
109 	FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4),
110 	FH(CLK_APMIXED_VCODECPLL, FH_VCODECPLL, 0xd8),
146 	base = devm_platform_ioremap_resource(pdev, 0);  in clk_mt6795_apmixed_probe()
178 	return 0;  in clk_mt6795_apmixed_probe()