Lines Matching full:parents

219 		.parents = { X1000_CLK_EXCLK },
242 		.parents = { X1000_CLK_EXCLK },
267 		.parents = { -1, -1, X1000_CLK_EXCLK, -1 },
275 		.parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
281 		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
292 		.parents = { X1000_CLK_CPUMUX },
304 		.parents = { X1000_CLK_CPUMUX },
310 		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
317 		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
323 		.parents = { X1000_CLK_AHB2PMUX },
329 		.parents = { X1000_CLK_AHB2PMUX },
337 		 * Disabling DDR clock or its parents will render DRAM
341 		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
349 		.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
357 		.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
363 		.parents = { X1000_CLK_I2SPLLMUX },
378 		.parents = { X1000_CLK_EXCLK, -1, -1, X1000_CLK_I2SPLL },
388 		.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
396 		.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
402 		.parents = { X1000_CLK_MSCMUX },
409 		.parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
416 		.parents = { X1000_CLK_EXCLK, -1, X1000_CLK_APLL, X1000_CLK_MPLL },
424 		.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
431 		.parents = { X1000_CLK_SSIPLL },
437 		.parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2 },
443 		.parents = { X1000_CLK_EXCLK },
449 		.parents = { X1000_CLK_EXCLK_DIV512, X1000_CLK_RTCLK },
458 		.parents = { X1000_CLK_AHB2 },
464 		.parents = { X1000_CLK_AHB2 },
470 		.parents = { X1000_CLK_SSIPLL },
476 		.parents = { X1000_CLK_PCLK },
482 		.parents = { X1000_CLK_PCLK },
488 		.parents = { X1000_CLK_PCLK },
494 		.parents = { X1000_CLK_EXCLK },
500 		.parents = { X1000_CLK_EXCLK },
506 		.parents = { X1000_CLK_EXCLK},
512 		.parents = { X1000_CLK_EXCLK },
518 		.parents = { X1000_CLK_EXCLK },
524 		.parents = { X1000_CLK_SSIMUX },
530 		.parents = { X1000_CLK_EXCLK },
536 		.parents = { X1000_CLK_EXCLK },