Lines Matching +full:power +full:- +full:gate
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
47 #define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */
53 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_enable()
54 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_enable()
63 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_disable()
64 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_disable()
72 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_is_enabled()
73 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_is_enabled()
86 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
142 .bypass_bit = -1,
159 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
167 CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
175 CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, 0,
178 .gate = { CGU_REG_CLKGR1, 7 },
184 CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
192 CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
195 .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
201 CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
212 .div = { CGU_REG_MSC0CDR, 0, 1, 7, -1, -1, 31 },
213 .gate = { CGU_REG_MSC0CDR, 31 },
219 .div = { CGU_REG_MSC1CDR, 0, 1, 7, -1, -1, 31 },
220 .gate = { CGU_REG_MSC1CDR, 31 },
226 .div = { CGU_REG_MSC2CDR, 0, 1, 7, -1, -1, 31 },
227 .gate = { CGU_REG_MSC2CDR, 31 },
233 .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
234 .gate = { CGU_REG_CLKGR0, 26 },
240 .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
241 .gate = { CGU_REG_CLKGR0, 24 },
245 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, -1 },
247 .div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 },
248 .gate = { CGU_REG_CLKGR1, 9 },
254 .div = { CGU_REG_BCHCDR, 0, 1, 3, -1, -1, -1 },
255 .gate = { CGU_REG_CLKGR0, 1 },
261 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
262 .gate = { CGU_REG_CLKGR0, 28 },
268 .div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 },
269 .gate = { CGU_REG_CLKGR0, 22 },
276 .parents = { JZ4770_CLK_EXT, -1,
279 .div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1 },
283 .parents = { JZ4770_CLK_EXT, -1,
286 .div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1 },
290 .parents = { JZ4770_CLK_EXT, -1,
293 .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
294 .gate = { CGU_REG_CLKGR1, 13 },
298 .parents = { JZ4770_CLK_EXT, -1,
301 .div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 },
302 .gate = { CGU_REG_CLKGR0, 2 },
305 /* Gate-only clocks */
310 .gate = { CGU_REG_CLKGR0, 4 },
315 .gate = { CGU_REG_CLKGR0, 19 },
320 .gate = { CGU_REG_CLKGR0, 20 },
325 .gate = { CGU_REG_CLKGR1, 8 },
330 .gate = { CGU_REG_CLKGR1, 10 },
335 .gate = { CGU_REG_CLKGR0, 21 },
340 .gate = { CGU_REG_CLKGR1, 0 },
345 .gate = { CGU_REG_CLKGR0, 5 },
350 .gate = { CGU_REG_CLKGR0, 6 },
355 .gate = { CGU_REG_CLKGR1, 15 },
360 .gate = { CGU_REG_CLKGR0, 15 },
365 .gate = { CGU_REG_CLKGR0, 16 },
370 .gate = { CGU_REG_CLKGR0, 17 },
375 .gate = { CGU_REG_CLKGR0, 18 },
380 .gate = { CGU_REG_CLKGR0, 29 },
385 .gate = { CGU_REG_CLKGR0, 14 },
390 .gate = { CGU_REG_CLKGR0, 8 },
395 .gate = { CGU_REG_CLKGR1, 14 },
400 .gate = { CGU_REG_LCR, 30, false, 150 },
405 .gate = { CGU_REG_CLKGR0, 3 },
410 .gate = { CGU_REG_CLKGR0, 11 },
415 .gate = { CGU_REG_CLKGR0, 12 },
420 .gate = { CGU_REG_OPCR, 7, true, 50 },
427 .parents = { JZ4770_CLK_UHC, -1, -1, -1 },
463 CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);