Lines Matching +full:jz4740 +full:- +full:adc
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Ingenic JZ4740 SoC CGU driver
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
51 0x0, 0x1, -1, 0x3,
71 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
96 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
98 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
110 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
112 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
119 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
121 CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
128 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
130 CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
142 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
144 CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
151 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
153 CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1, 0,
161 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
162 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
167 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
169 .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
175 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
177 .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
183 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
184 .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
190 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
191 .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
197 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
199 .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
203 /* Gate-only clocks */
207 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
213 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
219 .parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
225 .parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
230 "adc", CGU_CLK_GATE,
231 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
237 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
243 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
249 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
271 CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);