Lines Matching +full:convert +full:- +full:rate
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2013-2015 Imagination Technologies
11 #include <linux/clk-provider.h>
30 return &clk->cgu->clock_info[clk->idx]; in to_clk_info()
34 * ingenic_cgu_gate_get() - get the value of clock gate register bit
39 * caller must hold cgu->lock.
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) in ingenic_cgu_gate_get()
48 ^ info->clear_to_gate; in ingenic_cgu_gate_get()
52 * ingenic_cgu_gate_set() - set the value of clock gate register bit
55 * @val: non-zero to gate a clock, otherwise zero
59 * The caller must hold cgu->lock.
65 u32 clkgr = readl(cgu->base + info->reg); in ingenic_cgu_gate_set()
67 if (val ^ info->clear_to_gate) in ingenic_cgu_gate_set()
68 clkgr |= BIT(info->bit); in ingenic_cgu_gate_set()
70 clkgr &= ~BIT(info->bit); in ingenic_cgu_gate_set()
72 writel(clkgr, cgu->base + info->reg); in ingenic_cgu_gate_set()
84 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_recalc_rate()
90 BUG_ON(clk_info->type != CGU_CLK_PLL); in ingenic_pll_recalc_rate()
91 pll_info = &clk_info->pll; in ingenic_pll_recalc_rate()
93 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_recalc_rate()
95 m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); in ingenic_pll_recalc_rate()
96 m += pll_info->m_offset; in ingenic_pll_recalc_rate()
97 n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); in ingenic_pll_recalc_rate()
98 n += pll_info->n_offset; in ingenic_pll_recalc_rate()
100 if (pll_info->od_bits > 0) { in ingenic_pll_recalc_rate()
101 od_enc = ctl >> pll_info->od_shift; in ingenic_pll_recalc_rate()
102 od_enc &= GENMASK(pll_info->od_bits - 1, 0); in ingenic_pll_recalc_rate()
105 if (pll_info->bypass_bit >= 0) { in ingenic_pll_recalc_rate()
106 ctl = readl(cgu->base + pll_info->bypass_reg); in ingenic_pll_recalc_rate()
108 bypass = !!(ctl & BIT(pll_info->bypass_bit)); in ingenic_pll_recalc_rate()
114 for (od = 0; od < pll_info->od_max; od++) in ingenic_pll_recalc_rate()
115 if (pll_info->od_encoding[od] == od_enc) in ingenic_pll_recalc_rate()
119 if (pll_info->od_max == 0) in ingenic_pll_recalc_rate()
120 BUG_ON(pll_info->od_bits != 0); in ingenic_pll_recalc_rate()
122 BUG_ON(od == pll_info->od_max); in ingenic_pll_recalc_rate()
125 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, in ingenic_pll_recalc_rate()
131 unsigned long rate, unsigned long parent_rate, in ingenic_pll_calc_m_n_od() argument
141 n = min_t(unsigned int, n, 1 << pll_info->n_bits); in ingenic_pll_calc_m_n_od()
142 n = max_t(unsigned int, n, pll_info->n_offset); in ingenic_pll_calc_m_n_od()
144 m = (rate / MHZ) * od * n / (parent_rate / MHZ); in ingenic_pll_calc_m_n_od()
145 m = min_t(unsigned int, m, 1 << pll_info->m_bits); in ingenic_pll_calc_m_n_od()
146 m = max_t(unsigned int, m, pll_info->m_offset); in ingenic_pll_calc_m_n_od()
155 unsigned long rate, unsigned long parent_rate, in ingenic_pll_calc() argument
158 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_calc()
161 if (pll_info->calc_m_n_od) in ingenic_pll_calc()
162 (*pll_info->calc_m_n_od)(pll_info, rate, parent_rate, &m, &n, &od); in ingenic_pll_calc()
164 ingenic_pll_calc_m_n_od(pll_info, rate, parent_rate, &m, &n, &od); in ingenic_pll_calc()
173 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, in ingenic_pll_calc()
192 if (pll_info->stable_bit < 0) in ingenic_pll_check_stable()
195 return readl_poll_timeout(cgu->base + pll_info->reg, ctl, in ingenic_pll_check_stable()
196 ctl & BIT(pll_info->stable_bit), in ingenic_pll_check_stable()
205 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_set_rate()
207 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_set_rate()
208 unsigned long rate, flags; in ingenic_pll_set_rate() local
213 rate = ingenic_pll_calc(clk_info, req_rate, parent_rate, in ingenic_pll_set_rate()
215 if (rate != req_rate) in ingenic_pll_set_rate()
216 pr_info("ingenic-cgu: request '%s' rate %luHz, actual %luHz\n", in ingenic_pll_set_rate()
217 clk_info->name, req_rate, rate); in ingenic_pll_set_rate()
219 spin_lock_irqsave(&cgu->lock, flags); in ingenic_pll_set_rate()
220 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_set_rate()
222 ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift); in ingenic_pll_set_rate()
223 ctl |= (m - pll_info->m_offset) << pll_info->m_shift; in ingenic_pll_set_rate()
225 ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift); in ingenic_pll_set_rate()
226 ctl |= (n - pll_info->n_offset) << pll_info->n_shift; in ingenic_pll_set_rate()
228 if (pll_info->od_bits > 0) { in ingenic_pll_set_rate()
229 ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); in ingenic_pll_set_rate()
230 ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; in ingenic_pll_set_rate()
233 writel(ctl, cgu->base + pll_info->reg); in ingenic_pll_set_rate()
235 if (pll_info->set_rate_hook) in ingenic_pll_set_rate()
236 pll_info->set_rate_hook(pll_info, rate, parent_rate); in ingenic_pll_set_rate()
239 if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit))) in ingenic_pll_set_rate()
242 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_pll_set_rate()
250 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_enable()
252 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_enable()
257 if (pll_info->enable_bit < 0) in ingenic_pll_enable()
260 spin_lock_irqsave(&cgu->lock, flags); in ingenic_pll_enable()
261 if (pll_info->bypass_bit >= 0) { in ingenic_pll_enable()
262 ctl = readl(cgu->base + pll_info->bypass_reg); in ingenic_pll_enable()
264 ctl &= ~BIT(pll_info->bypass_bit); in ingenic_pll_enable()
266 writel(ctl, cgu->base + pll_info->bypass_reg); in ingenic_pll_enable()
269 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_enable()
271 ctl |= BIT(pll_info->enable_bit); in ingenic_pll_enable()
273 writel(ctl, cgu->base + pll_info->reg); in ingenic_pll_enable()
276 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_pll_enable()
284 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_disable()
286 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_disable()
290 if (pll_info->enable_bit < 0) in ingenic_pll_disable()
293 spin_lock_irqsave(&cgu->lock, flags); in ingenic_pll_disable()
294 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_disable()
296 ctl &= ~BIT(pll_info->enable_bit); in ingenic_pll_disable()
298 writel(ctl, cgu->base + pll_info->reg); in ingenic_pll_disable()
299 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_pll_disable()
305 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_is_enabled()
307 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_is_enabled()
310 if (pll_info->enable_bit < 0) in ingenic_pll_is_enabled()
313 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_is_enabled()
315 return !!(ctl & BIT(pll_info->enable_bit)); in ingenic_pll_is_enabled()
329 * Operations for all non-PLL clocks
336 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_get_parent()
340 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_get_parent()
341 reg = readl(cgu->base + clk_info->mux.reg); in ingenic_clk_get_parent()
342 hw_idx = (reg >> clk_info->mux.shift) & in ingenic_clk_get_parent()
343 GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_get_parent()
346 * Convert the hardware index to the parent index by skipping in ingenic_clk_get_parent()
347 * over any -1's in the parents array. in ingenic_clk_get_parent()
350 if (clk_info->parents[i] != -1) in ingenic_clk_get_parent()
362 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_set_parent()
367 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_set_parent()
369 * Convert the parent index to the hardware index by adding in ingenic_clk_set_parent()
370 * 1 for any -1 in the parents array preceding the given in ingenic_clk_set_parent()
372 * clk_info->parents which does not equal -1. in ingenic_clk_set_parent()
375 num_poss = 1 << clk_info->mux.bits; in ingenic_clk_set_parent()
377 if (clk_info->parents[hw_idx] == -1) in ingenic_clk_set_parent()
387 mask = GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_set_parent()
388 mask <<= clk_info->mux.shift; in ingenic_clk_set_parent()
390 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_set_parent()
393 reg = readl(cgu->base + clk_info->mux.reg); in ingenic_clk_set_parent()
395 reg |= hw_idx << clk_info->mux.shift; in ingenic_clk_set_parent()
396 writel(reg, cgu->base + clk_info->mux.reg); in ingenic_clk_set_parent()
398 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_set_parent()
402 return idx ? -EINVAL : 0; in ingenic_clk_set_parent()
410 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_recalc_rate()
411 unsigned long rate = parent_rate; in ingenic_clk_recalc_rate() local
415 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_recalc_rate()
418 if (!(clk_info->div.bypass_mask & BIT(parent))) { in ingenic_clk_recalc_rate()
419 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
420 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
421 GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_recalc_rate()
423 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
424 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
426 div = (div + 1) * clk_info->div.div; in ingenic_clk_recalc_rate()
428 rate /= div; in ingenic_clk_recalc_rate()
430 } else if (clk_info->type & CGU_CLK_FIXDIV) { in ingenic_clk_recalc_rate()
431 rate /= clk_info->fixdiv.div; in ingenic_clk_recalc_rate()
434 return rate; in ingenic_clk_recalc_rate()
441 unsigned int i, best_i = 0, best = (unsigned int)-1; in ingenic_clk_calc_hw_div()
443 for (i = 0; i < (1 << clk_info->div.bits) in ingenic_clk_calc_hw_div()
444 && clk_info->div.div_table[i]; i++) { in ingenic_clk_calc_hw_div()
445 if (clk_info->div.div_table[i] >= div && in ingenic_clk_calc_hw_div()
446 clk_info->div.div_table[i] < best) { in ingenic_clk_calc_hw_div()
447 best = clk_info->div.div_table[i]; in ingenic_clk_calc_hw_div()
467 if (clk_info->div.bypass_mask & BIT(parent)) in ingenic_clk_calc_div()
473 if (clk_info->div.div_table) { in ingenic_clk_calc_div()
476 return clk_info->div.div_table[hw_div]; in ingenic_clk_calc_div()
480 div = clamp_t(unsigned int, div, clk_info->div.div, in ingenic_clk_calc_div()
481 clk_info->div.div << clk_info->div.bits); in ingenic_clk_calc_div()
488 div = DIV_ROUND_UP(div, clk_info->div.div); in ingenic_clk_calc_div()
489 div *= clk_info->div.div; in ingenic_clk_calc_div()
501 if (clk_info->type & CGU_CLK_DIV) in ingenic_clk_determine_rate()
502 div = ingenic_clk_calc_div(hw, clk_info, req->best_parent_rate, in ingenic_clk_determine_rate()
503 req->rate); in ingenic_clk_determine_rate()
504 else if (clk_info->type & CGU_CLK_FIXDIV) in ingenic_clk_determine_rate()
505 div = clk_info->fixdiv.div; in ingenic_clk_determine_rate()
507 req->best_parent_rate = req->rate; in ingenic_clk_determine_rate()
509 req->rate = DIV_ROUND_UP(req->best_parent_rate, div); in ingenic_clk_determine_rate()
518 return readl_poll_timeout(cgu->base + clk_info->div.reg, reg, in ingenic_clk_check_stable()
519 !(reg & BIT(clk_info->div.busy_bit)), in ingenic_clk_check_stable()
529 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_set_rate()
530 unsigned long rate, flags; in ingenic_clk_set_rate() local
535 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_set_rate()
537 rate = DIV_ROUND_UP(parent_rate, div); in ingenic_clk_set_rate()
539 if (rate != req_rate) in ingenic_clk_set_rate()
540 return -EINVAL; in ingenic_clk_set_rate()
542 if (clk_info->div.div_table) in ingenic_clk_set_rate()
545 hw_div = ((div / clk_info->div.div) - 1); in ingenic_clk_set_rate()
547 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_set_rate()
548 reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_set_rate()
551 mask = GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_set_rate()
552 reg &= ~(mask << clk_info->div.shift); in ingenic_clk_set_rate()
553 reg |= hw_div << clk_info->div.shift; in ingenic_clk_set_rate()
556 if (clk_info->div.stop_bit != -1) in ingenic_clk_set_rate()
557 reg &= ~BIT(clk_info->div.stop_bit); in ingenic_clk_set_rate()
560 if (clk_info->div.ce_bit != -1) in ingenic_clk_set_rate()
561 reg |= BIT(clk_info->div.ce_bit); in ingenic_clk_set_rate()
564 writel(reg, cgu->base + clk_info->div.reg); in ingenic_clk_set_rate()
567 if (clk_info->div.busy_bit != -1) in ingenic_clk_set_rate()
570 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_set_rate()
574 return -EINVAL; in ingenic_clk_set_rate()
581 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_enable()
584 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_enable()
586 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_enable()
587 ingenic_cgu_gate_set(cgu, &clk_info->gate, false); in ingenic_clk_enable()
588 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_enable()
590 if (clk_info->gate.delay_us) in ingenic_clk_enable()
591 udelay(clk_info->gate.delay_us); in ingenic_clk_enable()
601 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_disable()
604 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_disable()
606 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_disable()
607 ingenic_cgu_gate_set(cgu, &clk_info->gate, true); in ingenic_clk_disable()
608 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_disable()
616 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_is_enabled()
619 if (clk_info->type & CGU_CLK_GATE) in ingenic_clk_is_enabled()
620 enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate); in ingenic_clk_is_enabled()
644 const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx]; in ingenic_register_clock()
650 int err = -EINVAL; in ingenic_register_clock()
652 BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names)); in ingenic_register_clock()
654 if (clk_info->type == CGU_CLK_EXT) { in ingenic_register_clock()
655 clk = of_clk_get_by_name(cgu->np, clk_info->name); in ingenic_register_clock()
658 __func__, clk_info->name); in ingenic_register_clock()
659 err = -ENODEV; in ingenic_register_clock()
662 err = clk_register_clkdev(clk, clk_info->name, NULL); in ingenic_register_clock()
667 cgu->clocks.clks[idx] = clk; in ingenic_register_clock()
671 if (!clk_info->type) { in ingenic_register_clock()
673 clk_info->name); in ingenic_register_clock()
679 err = -ENOMEM; in ingenic_register_clock()
683 ingenic_clk->hw.init = &clk_init; in ingenic_register_clock()
684 ingenic_clk->cgu = cgu; in ingenic_register_clock()
685 ingenic_clk->idx = idx; in ingenic_register_clock()
687 clk_init.name = clk_info->name; in ingenic_register_clock()
688 clk_init.flags = clk_info->flags; in ingenic_register_clock()
691 caps = clk_info->type; in ingenic_register_clock()
696 /* pass rate changes to the parent clock */ in ingenic_register_clock()
704 num_possible = 1 << clk_info->mux.bits; in ingenic_register_clock()
706 num_possible = ARRAY_SIZE(clk_info->parents); in ingenic_register_clock()
709 if (clk_info->parents[i] == -1) in ingenic_register_clock()
712 parent = cgu->clocks.clks[clk_info->parents[i]]; in ingenic_register_clock()
721 BUG_ON(clk_info->parents[0] == -1); in ingenic_register_clock()
723 parent = cgu->clocks.clks[clk_info->parents[0]]; in ingenic_register_clock()
728 clk_init.ops = clk_info->custom.clk_ops; in ingenic_register_clock()
766 clk = clk_register(NULL, &ingenic_clk->hw); in ingenic_register_clock()
769 clk_info->name); in ingenic_register_clock()
774 err = clk_register_clkdev(clk, clk_info->name, NULL); in ingenic_register_clock()
778 cgu->clocks.clks[idx] = clk; in ingenic_register_clock()
795 cgu->base = of_iomap(np, 0); in ingenic_cgu_new()
796 if (!cgu->base) { in ingenic_cgu_new()
801 cgu->np = np; in ingenic_cgu_new()
802 cgu->clock_info = clock_info; in ingenic_cgu_new()
803 cgu->clocks.clk_num = num_clocks; in ingenic_cgu_new()
805 spin_lock_init(&cgu->lock); in ingenic_cgu_new()
820 cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *), in ingenic_cgu_register_clocks()
822 if (!cgu->clocks.clks) { in ingenic_cgu_register_clocks()
823 err = -ENOMEM; in ingenic_cgu_register_clocks()
827 for (i = 0; i < cgu->clocks.clk_num; i++) { in ingenic_cgu_register_clocks()
833 err = of_clk_add_provider(cgu->np, of_clk_src_onecell_get, in ingenic_cgu_register_clocks()
834 &cgu->clocks); in ingenic_cgu_register_clocks()
841 for (i = 0; i < cgu->clocks.clk_num; i++) { in ingenic_cgu_register_clocks()
842 if (!cgu->clocks.clks[i]) in ingenic_cgu_register_clocks()
844 if (cgu->clock_info[i].type & CGU_CLK_EXT) in ingenic_cgu_register_clocks()
845 clk_put(cgu->clocks.clks[i]); in ingenic_cgu_register_clocks()
847 clk_unregister(cgu->clocks.clks[i]); in ingenic_cgu_register_clocks()
849 kfree(cgu->clocks.clks); in ingenic_cgu_register_clocks()