Lines Matching +full:clk +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2013-2015 Imagination Technologies
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
28 to_clk_info(struct ingenic_clk *clk) in to_clk_info() argument
30 return &clk->cgu->clock_info[clk->idx]; in to_clk_info()
34 * ingenic_cgu_gate_get() - get the value of clock gate register bit
39 * caller must hold cgu->lock.
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) in ingenic_cgu_gate_get()
48 ^ info->clear_to_gate; in ingenic_cgu_gate_get()
52 * ingenic_cgu_gate_set() - set the value of clock gate register bit
55 * @val: non-zero to gate a clock, otherwise zero
59 * The caller must hold cgu->lock.
65 u32 clkgr = readl(cgu->base + info->reg); in ingenic_cgu_gate_set()
67 if (val ^ info->clear_to_gate) in ingenic_cgu_gate_set()
68 clkgr |= BIT(info->bit); in ingenic_cgu_gate_set()
70 clkgr &= ~BIT(info->bit); in ingenic_cgu_gate_set()
72 writel(clkgr, cgu->base + info->reg); in ingenic_cgu_gate_set()
84 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_recalc_rate()
90 BUG_ON(clk_info->type != CGU_CLK_PLL); in ingenic_pll_recalc_rate()
91 pll_info = &clk_info->pll; in ingenic_pll_recalc_rate()
93 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_recalc_rate()
95 m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); in ingenic_pll_recalc_rate()
96 m += pll_info->m_offset; in ingenic_pll_recalc_rate()
97 n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); in ingenic_pll_recalc_rate()
98 n += pll_info->n_offset; in ingenic_pll_recalc_rate()
100 if (pll_info->od_bits > 0) { in ingenic_pll_recalc_rate()
101 od_enc = ctl >> pll_info->od_shift; in ingenic_pll_recalc_rate()
102 od_enc &= GENMASK(pll_info->od_bits - 1, 0); in ingenic_pll_recalc_rate()
105 if (pll_info->bypass_bit >= 0) { in ingenic_pll_recalc_rate()
106 ctl = readl(cgu->base + pll_info->bypass_reg); in ingenic_pll_recalc_rate()
108 bypass = !!(ctl & BIT(pll_info->bypass_bit)); in ingenic_pll_recalc_rate()
114 for (od = 0; od < pll_info->od_max; od++) in ingenic_pll_recalc_rate()
115 if (pll_info->od_encoding[od] == od_enc) in ingenic_pll_recalc_rate()
119 if (pll_info->od_max == 0) in ingenic_pll_recalc_rate()
120 BUG_ON(pll_info->od_bits != 0); in ingenic_pll_recalc_rate()
122 BUG_ON(od == pll_info->od_max); in ingenic_pll_recalc_rate()
125 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, in ingenic_pll_recalc_rate()
141 n = min_t(unsigned int, n, 1 << pll_info->n_bits); in ingenic_pll_calc_m_n_od()
142 n = max_t(unsigned int, n, pll_info->n_offset); in ingenic_pll_calc_m_n_od()
145 m = min_t(unsigned int, m, 1 << pll_info->m_bits); in ingenic_pll_calc_m_n_od()
146 m = max_t(unsigned int, m, pll_info->m_offset); in ingenic_pll_calc_m_n_od()
158 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_calc()
161 if (pll_info->calc_m_n_od) in ingenic_pll_calc()
162 (*pll_info->calc_m_n_od)(pll_info, rate, parent_rate, &m, &n, &od); in ingenic_pll_calc()
173 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, in ingenic_pll_calc()
183 req->rate = ingenic_pll_calc(clk_info, req->rate, req->best_parent_rate, in ingenic_pll_determine_rate()
194 if (pll_info->stable_bit < 0) in ingenic_pll_check_stable()
197 return readl_poll_timeout(cgu->base + pll_info->reg, ctl, in ingenic_pll_check_stable()
198 ctl & BIT(pll_info->stable_bit), in ingenic_pll_check_stable()
207 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_set_rate()
209 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_set_rate()
218 pr_info("ingenic-cgu: request '%s' rate %luHz, actual %luHz\n", in ingenic_pll_set_rate()
219 clk_info->name, req_rate, rate); in ingenic_pll_set_rate()
221 spin_lock_irqsave(&cgu->lock, flags); in ingenic_pll_set_rate()
222 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_set_rate()
224 ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift); in ingenic_pll_set_rate()
225 ctl |= (m - pll_info->m_offset) << pll_info->m_shift; in ingenic_pll_set_rate()
227 ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift); in ingenic_pll_set_rate()
228 ctl |= (n - pll_info->n_offset) << pll_info->n_shift; in ingenic_pll_set_rate()
230 if (pll_info->od_bits > 0) { in ingenic_pll_set_rate()
231 ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); in ingenic_pll_set_rate()
232 ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; in ingenic_pll_set_rate()
235 writel(ctl, cgu->base + pll_info->reg); in ingenic_pll_set_rate()
237 if (pll_info->set_rate_hook) in ingenic_pll_set_rate()
238 pll_info->set_rate_hook(pll_info, rate, parent_rate); in ingenic_pll_set_rate()
241 if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit))) in ingenic_pll_set_rate()
244 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_pll_set_rate()
252 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_enable()
254 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_enable()
259 if (pll_info->enable_bit < 0) in ingenic_pll_enable()
262 spin_lock_irqsave(&cgu->lock, flags); in ingenic_pll_enable()
263 if (pll_info->bypass_bit >= 0) { in ingenic_pll_enable()
264 ctl = readl(cgu->base + pll_info->bypass_reg); in ingenic_pll_enable()
266 ctl &= ~BIT(pll_info->bypass_bit); in ingenic_pll_enable()
268 writel(ctl, cgu->base + pll_info->bypass_reg); in ingenic_pll_enable()
271 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_enable()
273 ctl |= BIT(pll_info->enable_bit); in ingenic_pll_enable()
275 writel(ctl, cgu->base + pll_info->reg); in ingenic_pll_enable()
278 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_pll_enable()
286 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_disable()
288 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_disable()
292 if (pll_info->enable_bit < 0) in ingenic_pll_disable()
295 spin_lock_irqsave(&cgu->lock, flags); in ingenic_pll_disable()
296 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_disable()
298 ctl &= ~BIT(pll_info->enable_bit); in ingenic_pll_disable()
300 writel(ctl, cgu->base + pll_info->reg); in ingenic_pll_disable()
301 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_pll_disable()
307 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_is_enabled()
309 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_is_enabled()
312 if (pll_info->enable_bit < 0) in ingenic_pll_is_enabled()
315 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_is_enabled()
317 return !!(ctl & BIT(pll_info->enable_bit)); in ingenic_pll_is_enabled()
331 * Operations for all non-PLL clocks
338 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_get_parent()
342 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_get_parent()
343 reg = readl(cgu->base + clk_info->mux.reg); in ingenic_clk_get_parent()
344 hw_idx = (reg >> clk_info->mux.shift) & in ingenic_clk_get_parent()
345 GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_get_parent()
349 * over any -1's in the parents array. in ingenic_clk_get_parent()
352 if (clk_info->parents[i] != -1) in ingenic_clk_get_parent()
364 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_set_parent()
369 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_set_parent()
372 * 1 for any -1 in the parents array preceding the given in ingenic_clk_set_parent()
374 * clk_info->parents which does not equal -1. in ingenic_clk_set_parent()
377 num_poss = 1 << clk_info->mux.bits; in ingenic_clk_set_parent()
379 if (clk_info->parents[hw_idx] == -1) in ingenic_clk_set_parent()
389 mask = GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_set_parent()
390 mask <<= clk_info->mux.shift; in ingenic_clk_set_parent()
392 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_set_parent()
395 reg = readl(cgu->base + clk_info->mux.reg); in ingenic_clk_set_parent()
397 reg |= hw_idx << clk_info->mux.shift; in ingenic_clk_set_parent()
398 writel(reg, cgu->base + clk_info->mux.reg); in ingenic_clk_set_parent()
400 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_set_parent()
404 return idx ? -EINVAL : 0; in ingenic_clk_set_parent()
412 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_recalc_rate()
414 u32 div_reg, div; in ingenic_clk_recalc_rate() local
417 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_recalc_rate()
420 if (!(clk_info->div.bypass_mask & BIT(parent))) { in ingenic_clk_recalc_rate()
421 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
422 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
423 GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_recalc_rate()
425 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
426 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
428 div = (div + 1) * clk_info->div.div; in ingenic_clk_recalc_rate()
430 rate /= div; in ingenic_clk_recalc_rate()
432 } else if (clk_info->type & CGU_CLK_FIXDIV) { in ingenic_clk_recalc_rate()
433 rate /= clk_info->fixdiv.div; in ingenic_clk_recalc_rate()
441 unsigned int div) in ingenic_clk_calc_hw_div() argument
443 unsigned int i, best_i = 0, best = (unsigned int)-1; in ingenic_clk_calc_hw_div()
445 for (i = 0; i < (1 << clk_info->div.bits) in ingenic_clk_calc_hw_div()
446 && clk_info->div.div_table[i]; i++) { in ingenic_clk_calc_hw_div()
447 if (clk_info->div.div_table[i] >= div && in ingenic_clk_calc_hw_div()
448 clk_info->div.div_table[i] < best) { in ingenic_clk_calc_hw_div()
449 best = clk_info->div.div_table[i]; in ingenic_clk_calc_hw_div()
452 if (div == best) in ingenic_clk_calc_hw_div()
465 unsigned int div, hw_div; in ingenic_clk_calc_div() local
469 if (clk_info->div.bypass_mask & BIT(parent)) in ingenic_clk_calc_div()
473 div = DIV_ROUND_UP(parent_rate, req_rate); in ingenic_clk_calc_div()
475 if (clk_info->div.div_table) { in ingenic_clk_calc_div()
476 hw_div = ingenic_clk_calc_hw_div(clk_info, div); in ingenic_clk_calc_div()
478 return clk_info->div.div_table[hw_div]; in ingenic_clk_calc_div()
482 div = clamp_t(unsigned int, div, clk_info->div.div, in ingenic_clk_calc_div()
483 clk_info->div.div << clk_info->div.bits); in ingenic_clk_calc_div()
490 div = DIV_ROUND_UP(div, clk_info->div.div); in ingenic_clk_calc_div()
491 div *= clk_info->div.div; in ingenic_clk_calc_div()
493 return div; in ingenic_clk_calc_div()
501 unsigned int div = 1; in ingenic_clk_determine_rate() local
503 if (clk_info->type & CGU_CLK_DIV) in ingenic_clk_determine_rate()
504 div = ingenic_clk_calc_div(hw, clk_info, req->best_parent_rate, in ingenic_clk_determine_rate()
505 req->rate); in ingenic_clk_determine_rate()
506 else if (clk_info->type & CGU_CLK_FIXDIV) in ingenic_clk_determine_rate()
507 div = clk_info->fixdiv.div; in ingenic_clk_determine_rate()
509 req->best_parent_rate = req->rate; in ingenic_clk_determine_rate()
511 req->rate = DIV_ROUND_UP(req->best_parent_rate, div); in ingenic_clk_determine_rate()
520 return readl_poll_timeout(cgu->base + clk_info->div.reg, reg, in ingenic_clk_check_stable()
521 !(reg & BIT(clk_info->div.busy_bit)), in ingenic_clk_check_stable()
531 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_set_rate()
533 unsigned int hw_div, div; in ingenic_clk_set_rate() local
537 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_set_rate()
538 div = ingenic_clk_calc_div(hw, clk_info, parent_rate, req_rate); in ingenic_clk_set_rate()
539 rate = DIV_ROUND_UP(parent_rate, div); in ingenic_clk_set_rate()
542 return -EINVAL; in ingenic_clk_set_rate()
544 if (clk_info->div.div_table) in ingenic_clk_set_rate()
545 hw_div = ingenic_clk_calc_hw_div(clk_info, div); in ingenic_clk_set_rate()
547 hw_div = ((div / clk_info->div.div) - 1); in ingenic_clk_set_rate()
549 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_set_rate()
550 reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_set_rate()
553 mask = GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_set_rate()
554 reg &= ~(mask << clk_info->div.shift); in ingenic_clk_set_rate()
555 reg |= hw_div << clk_info->div.shift; in ingenic_clk_set_rate()
558 if (clk_info->div.stop_bit != -1) in ingenic_clk_set_rate()
559 reg &= ~BIT(clk_info->div.stop_bit); in ingenic_clk_set_rate()
562 if (clk_info->div.ce_bit != -1) in ingenic_clk_set_rate()
563 reg |= BIT(clk_info->div.ce_bit); in ingenic_clk_set_rate()
566 writel(reg, cgu->base + clk_info->div.reg); in ingenic_clk_set_rate()
569 if (clk_info->div.busy_bit != -1) in ingenic_clk_set_rate()
572 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_set_rate()
576 return -EINVAL; in ingenic_clk_set_rate()
583 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_enable()
586 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_enable()
588 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_enable()
589 ingenic_cgu_gate_set(cgu, &clk_info->gate, false); in ingenic_clk_enable()
590 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_enable()
592 if (clk_info->gate.delay_us) in ingenic_clk_enable()
593 udelay(clk_info->gate.delay_us); in ingenic_clk_enable()
603 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_disable()
606 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_disable()
608 spin_lock_irqsave(&cgu->lock, flags); in ingenic_clk_disable()
609 ingenic_cgu_gate_set(cgu, &clk_info->gate, true); in ingenic_clk_disable()
610 spin_unlock_irqrestore(&cgu->lock, flags); in ingenic_clk_disable()
618 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_is_enabled()
621 if (clk_info->type & CGU_CLK_GATE) in ingenic_clk_is_enabled()
622 enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate); in ingenic_clk_is_enabled()
646 const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx]; in ingenic_register_clock()
649 struct clk *clk, *parent; in ingenic_register_clock() local
652 int err = -EINVAL; in ingenic_register_clock()
654 BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names)); in ingenic_register_clock()
656 if (clk_info->type == CGU_CLK_EXT) { in ingenic_register_clock()
657 clk = of_clk_get_by_name(cgu->np, clk_info->name); in ingenic_register_clock()
658 if (IS_ERR(clk)) { in ingenic_register_clock()
660 __func__, clk_info->name); in ingenic_register_clock()
661 err = -ENODEV; in ingenic_register_clock()
664 err = clk_register_clkdev(clk, clk_info->name, NULL); in ingenic_register_clock()
666 clk_put(clk); in ingenic_register_clock()
669 cgu->clocks.clks[idx] = clk; in ingenic_register_clock()
673 if (!clk_info->type) { in ingenic_register_clock()
675 clk_info->name); in ingenic_register_clock()
681 err = -ENOMEM; in ingenic_register_clock()
685 ingenic_clk->hw.init = &clk_init; in ingenic_register_clock()
686 ingenic_clk->cgu = cgu; in ingenic_register_clock()
687 ingenic_clk->idx = idx; in ingenic_register_clock()
689 clk_init.name = clk_info->name; in ingenic_register_clock()
690 clk_init.flags = clk_info->flags; in ingenic_register_clock()
693 caps = clk_info->type; in ingenic_register_clock()
706 num_possible = 1 << clk_info->mux.bits; in ingenic_register_clock()
708 num_possible = ARRAY_SIZE(clk_info->parents); in ingenic_register_clock()
711 if (clk_info->parents[i] == -1) in ingenic_register_clock()
714 parent = cgu->clocks.clks[clk_info->parents[i]]; in ingenic_register_clock()
723 BUG_ON(clk_info->parents[0] == -1); in ingenic_register_clock()
725 parent = cgu->clocks.clks[clk_info->parents[0]]; in ingenic_register_clock()
730 clk_init.ops = clk_info->custom.clk_ops; in ingenic_register_clock()
768 clk = clk_register(NULL, &ingenic_clk->hw); in ingenic_register_clock()
769 if (IS_ERR(clk)) { in ingenic_register_clock()
771 clk_info->name); in ingenic_register_clock()
772 err = PTR_ERR(clk); in ingenic_register_clock()
776 err = clk_register_clkdev(clk, clk_info->name, NULL); in ingenic_register_clock()
780 cgu->clocks.clks[idx] = clk; in ingenic_register_clock()
797 cgu->base = of_iomap(np, 0); in ingenic_cgu_new()
798 if (!cgu->base) { in ingenic_cgu_new()
803 cgu->np = np; in ingenic_cgu_new()
804 cgu->clock_info = clock_info; in ingenic_cgu_new()
805 cgu->clocks.clk_num = num_clocks; in ingenic_cgu_new()
807 spin_lock_init(&cgu->lock); in ingenic_cgu_new()
822 cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *), in ingenic_cgu_register_clocks()
824 if (!cgu->clocks.clks) { in ingenic_cgu_register_clocks()
825 err = -ENOMEM; in ingenic_cgu_register_clocks()
829 for (i = 0; i < cgu->clocks.clk_num; i++) { in ingenic_cgu_register_clocks()
835 err = of_clk_add_provider(cgu->np, of_clk_src_onecell_get, in ingenic_cgu_register_clocks()
836 &cgu->clocks); in ingenic_cgu_register_clocks()
843 for (i = 0; i < cgu->clocks.clk_num; i++) { in ingenic_cgu_register_clocks()
844 if (!cgu->clocks.clks[i]) in ingenic_cgu_register_clocks()
846 if (cgu->clock_info[i].type & CGU_CLK_EXT) in ingenic_cgu_register_clocks()
847 clk_put(cgu->clocks.clks[i]); in ingenic_cgu_register_clocks()
849 clk_unregister(cgu->clocks.clks[i]); in ingenic_cgu_register_clocks()
851 kfree(cgu->clocks.clks); in ingenic_cgu_register_clocks()