Lines Matching +full:scu +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2021 NXP
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
10 #include <linux/clk-provider.h>
20 #include "clk-scu.h"
44 * struct clk_scu - Description of one SCU clock
46 * @rsrc_id: resource ID of this SCU clock
62 * struct clk_gpr_scu - Description of one SCU GPR clock
64 * @rsrc_id: resource ID of this SCU clock
78 * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
79 * @hdr: SCU protocol header
82 * @clk: clk type of this resource
84 * This structure describes the SCU protocol of clock rate set
90 u8 clk;
95 u8 clk;
103 * struct imx_sc_msg_get_clock_rate - clock get rate protocol
104 * @hdr: SCU protocol header
108 * This structure describes the SCU protocol of clock rate get
119 * struct imx_sc_msg_get_clock_parent - clock get parent protocol
120 * @hdr: SCU protocol header
124 * This structure describes the SCU protocol of clock get parent
131 u8 clk;
140 * struct imx_sc_msg_set_clock_parent - clock set parent protocol
141 * @hdr: SCU protocol header
144 * This structure describes the SCU protocol of clock set parent
149 u8 clk;
154 * struct imx_sc_msg_req_clock_enable - clock gate protocol
155 * @hdr: SCU protocol header
157 * @clk: clk type of this resource
161 * This structure describes the SCU protocol of clock gate
166 u8 clk;
178 return *(u32 *)rsrc - *(u32 *)rsrc_p;
188 p = bsearch(&rsrc_id, rsrc_table->rsrc, rsrc_table->num,
189 sizeof(rsrc_table->rsrc[0]), imx_scu_clk_search_cmp);
204 of_property_read_u32(np, "#clock-cells", &clk_cells);
211 pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd");
213 return -EINVAL;
222 * clk_scu_recalc_rate - Get clock rate for a SCU clock
226 * Gets the current clock rate of a SCU clock. Returns the current
232 struct clk_scu *clk = to_clk_scu(hw);
237 hdr->ver = IMX_SC_RPC_VERSION;
238 hdr->svc = IMX_SC_RPC_SVC_PM;
239 hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_RATE;
240 hdr->size = 2;
242 msg.data.req.resource = cpu_to_le16(clk->rsrc_id);
243 msg.data.req.clk = clk->clk_type;
256 * clk_scu_determine_rate - Returns the closest rate for a SCU clock
266 * Assume we support all the requested rate and let the SCU firmware
275 struct clk_scu *clk = to_clk_scu(hw);
279 if (clk->rsrc_id == IMX_SC_R_A35 || clk->rsrc_id == IMX_SC_R_A53)
281 else if (clk->rsrc_id == IMX_SC_R_A72)
284 return -EINVAL;
286 /* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */
294 * clk_scu_set_rate - Set rate for a SCU clock
297 * @parent_rate: rate of the clock parent, not used for SCU clocks
299 * Sets a clock frequency for a SCU clock. Returns the SCU
305 struct clk_scu *clk = to_clk_scu(hw);
309 hdr->ver = IMX_SC_RPC_VERSION;
310 hdr->svc = IMX_SC_RPC_SVC_PM;
311 hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_RATE;
312 hdr->size = 3;
315 msg.resource = cpu_to_le16(clk->rsrc_id);
316 msg.clk = clk->clk_type;
323 struct clk_scu *clk = to_clk_scu(hw);
328 hdr->ver = IMX_SC_RPC_VERSION;
329 hdr->svc = IMX_SC_RPC_SVC_PM;
330 hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_PARENT;
331 hdr->size = 2;
333 msg.data.req.resource = cpu_to_le16(clk->rsrc_id);
334 msg.data.req.clk = clk->clk_type;
343 clk->parent_index = msg.data.resp.parent;
350 struct clk_scu *clk = to_clk_scu(hw);
355 hdr->ver = IMX_SC_RPC_VERSION;
356 hdr->svc = IMX_SC_RPC_SVC_PM;
357 hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_PARENT;
358 hdr->size = 2;
360 msg.resource = cpu_to_le16(clk->rsrc_id);
361 msg.clk = clk->clk_type;
371 clk->parent_index = index;
377 u8 clk, bool enable, bool autog)
382 hdr->ver = IMX_SC_RPC_VERSION;
383 hdr->svc = IMX_SC_RPC_SVC_PM;
384 hdr->func = IMX_SC_PM_FUNC_CLOCK_ENABLE;
385 hdr->size = 3;
388 msg.clk = clk;
396 * clk_scu_prepare - Enable a SCU clock
403 struct clk_scu *clk = to_clk_scu(hw);
405 return sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,
406 clk->clk_type, true, false);
410 * clk_scu_unprepare - Disable a SCU clock
417 struct clk_scu *clk = to_clk_scu(hw);
420 ret = sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,
421 clk->clk_type, false, false);
423 pr_warn("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
456 struct clk_scu *clk;
460 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
461 if (!clk)
462 return ERR_PTR(-ENOMEM);
464 clk->rsrc_id = rsrc_id;
465 clk->clk_type = clk_type;
486 clk->hw.init = &init;
488 hw = &clk->hw;
491 kfree(clk);
497 dev_set_drvdata(dev, clk);
505 unsigned int rsrc = clkspec->args[0];
506 unsigned int idx = clkspec->args[1];
508 struct imx_scu_clk_node *clk;
510 list_for_each_entry(clk, &scu_clks[rsrc], node) {
511 if (clk->clk_type == idx)
512 return clk->hw;
515 return ERR_PTR(-ENODEV);
520 struct device *dev = &pdev->dev;
521 struct imx_scu_clk_node *clk = dev_get_platdata(dev);
525 if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||
526 (clk->rsrc == IMX_SC_R_A72))) {
529 pm_runtime_use_autosuspend(&pdev->dev);
540 hw = __imx_clk_scu(dev, clk->name, clk->parents, clk->num_parents,
541 clk->rsrc, clk->clk_type);
547 clk->hw = hw;
548 list_add_tail(&clk->node, &imx_scu_clks[clk->rsrc]);
550 if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||
551 (clk->rsrc == IMX_SC_R_A72))) {
552 pm_runtime_put_autosuspend(&pdev->dev);
555 dev_dbg(dev, "register SCU clock rsrc:%d type:%d\n", clk->rsrc,
556 clk->clk_type);
563 struct clk_scu *clk = dev_get_drvdata(dev);
564 u32 rsrc_id = clk->rsrc_id;
570 clk->parent = clk_hw_get_parent(&clk->hw);
572 /* DC SS needs to handle bypass clock using non-cached clock rate */
573 if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 ||
574 clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 ||
575 clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 ||
576 clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1)
577 clk->rate = clk_scu_recalc_rate(&clk->hw, 0);
579 clk->rate = clk_hw_get_rate(&clk->hw);
580 clk->is_enabled = clk_hw_is_prepared(&clk->hw);
582 if (clk->parent)
583 dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent),
584 clk->parent_index);
586 if (clk->rate)
587 dev_dbg(dev, "save rate %d\n", clk->rate);
589 if (clk->is_enabled)
597 struct clk_scu *clk = dev_get_drvdata(dev);
598 u32 rsrc_id = clk->rsrc_id;
605 if (clk->parent) {
606 ret = clk_scu_set_parent(&clk->hw, clk->parent_index);
608 clk_hw_get_name(clk->parent),
609 clk->parent_index, !ret ? "success" : "failed");
612 if (clk->rate) {
613 ret = clk_scu_set_rate(&clk->hw, clk->rate, 0);
614 dev_dbg(dev, "restore rate %d %s\n", clk->rate,
618 if (clk->is_enabled && rsrc_id != IMX_SC_R_PI_0_PLL) {
619 ret = clk_scu_prepare(&clk->hw);
634 .name = "imx-scu-clk",
659 * A-core resources are special. SCFW reports they are not "owned" by
672 struct imx_scu_clk_node clk = {
683 return ERR_PTR(-EINVAL);
690 pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n",
692 return ERR_PTR(-ENOMEM);
695 ret = platform_device_add_data(pdev, &clk, sizeof(clk));
699 ret = driver_set_override(&pdev->dev, &pdev->driver_override,
700 "imx-scu-clk", strlen("imx-scu-clk"));
704 ret = imx_clk_scu_attach_pd(&pdev->dev, rsrc_id);
723 struct imx_scu_clk_node *clk, *n;
727 list_for_each_entry_safe(clk, n, &imx_scu_clks[i], node) {
728 clk_hw_unregister(clk->hw);
729 kfree(clk);
737 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
742 err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
743 clk->gpr_id, &val);
753 if (req->rate < req->best_parent_rate)
754 req->rate = req->best_parent_rate / 2;
756 req->rate = req->best_parent_rate;
764 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
769 err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
770 clk->gpr_id, val);
772 return err ? -EINVAL : 0;
783 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
786 imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
787 clk->gpr_id, &val);
794 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
796 return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
797 clk->gpr_id, index);
808 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
810 return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
811 clk->gpr_id, !clk->gate_invert);
816 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
819 ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
820 clk->gpr_id, clk->gate_invert);
822 pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
828 struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
832 ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
833 clk->gpr_id, &val);
837 return clk->gate_invert ? !val : val;
851 struct clk_gpr_scu *clk;
857 return ERR_PTR(-EINVAL);
861 return ERR_PTR(-ENOMEM);
865 return ERR_PTR(-EINVAL);
873 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
874 if (!clk) {
876 return ERR_PTR(-ENOMEM);
879 clk->rsrc_id = rsrc_id;
880 clk->gpr_id = gpr_id;
881 clk->flags = flags;
882 clk->gate_invert = invert;
898 clk->hw.init = &init;
900 hw = &clk->hw;
903 kfree(clk);
907 clk_node->hw = hw;
908 clk_node->clk_type = gpr_id;
909 list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]);