1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2018-2021 NXP
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
10 #include <linux/clk-provider.h>
20 #include "clk-scu.h"
38 	struct list_head node;  member
44  * struct clk_scu - Description of one SCU clock
62  * struct clk_gpr_scu - Description of one SCU GPR clock
78  * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
79  * @hdr: SCU protocol header
84  * This structure describes the SCU protocol of clock rate set
103  * struct imx_sc_msg_get_clock_rate - clock get rate protocol
104  * @hdr: SCU protocol header
105  * @req: get rate request protocol
106  * @resp: get rate response protocol
108  * This structure describes the SCU protocol of clock rate get
119  * struct imx_sc_msg_get_clock_parent - clock get parent protocol
120  * @hdr: SCU protocol header
121  * @req: get parent request protocol
122  * @resp: get parent response protocol
124  * This structure describes the SCU protocol of clock get parent
140  * struct imx_sc_msg_set_clock_parent - clock set parent protocol
141  * @hdr: SCU protocol header
142  * @req: set parent request protocol
144  * This structure describes the SCU protocol of clock set parent
154  * struct imx_sc_msg_req_clock_enable - clock gate protocol
155  * @hdr: SCU protocol header
161  * This structure describes the SCU protocol of clock gate
178 	return *(u32 *)rsrc - *(u32 *)rsrc_p;  in imx_scu_clk_search_cmp()
188 	p = bsearch(&rsrc_id, rsrc_table->rsrc, rsrc_table->num,  in imx_scu_clk_is_valid()
189 		    sizeof(rsrc_table->rsrc[0]), imx_scu_clk_search_cmp);  in imx_scu_clk_is_valid()
204 	of_property_read_u32(np, "#clock-cells", &clk_cells);  in imx_clk_scu_init()
211 		pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd");  in imx_clk_scu_init()
213 			return -EINVAL;  in imx_clk_scu_init()
222  * clk_scu_recalc_rate - Get clock rate for a SCU clock
237 	hdr->ver = IMX_SC_RPC_VERSION;  in clk_scu_recalc_rate()
238 	hdr->svc = IMX_SC_RPC_SVC_PM;  in clk_scu_recalc_rate()
239 	hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_RATE;  in clk_scu_recalc_rate()
240 	hdr->size = 2;  in clk_scu_recalc_rate()
242 	msg.data.req.resource = cpu_to_le16(clk->rsrc_id);  in clk_scu_recalc_rate()
243 	msg.data.req.clk = clk->clk_type;  in clk_scu_recalc_rate()
256  * clk_scu_determine_rate - Returns the closest rate for a SCU clock
273  * clk_scu_round_rate - Round clock rate for a SCU clock
297 	if (clk->rsrc_id == IMX_SC_R_A35 || clk->rsrc_id == IMX_SC_R_A53)  in clk_scu_atf_set_cpu_rate()
299 	else if (clk->rsrc_id == IMX_SC_R_A72)  in clk_scu_atf_set_cpu_rate()
302 		return -EINVAL;  in clk_scu_atf_set_cpu_rate()
304 	/* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */  in clk_scu_atf_set_cpu_rate()
312  * clk_scu_set_rate - Set rate for a SCU clock
318  * protocol status.
327 	hdr->ver = IMX_SC_RPC_VERSION;  in clk_scu_set_rate()
328 	hdr->svc = IMX_SC_RPC_SVC_PM;  in clk_scu_set_rate()
329 	hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_RATE;  in clk_scu_set_rate()
330 	hdr->size = 3;  in clk_scu_set_rate()
333 	msg.resource = cpu_to_le16(clk->rsrc_id);  in clk_scu_set_rate()
334 	msg.clk = clk->clk_type;  in clk_scu_set_rate()
346 	hdr->ver = IMX_SC_RPC_VERSION;  in clk_scu_get_parent()
347 	hdr->svc = IMX_SC_RPC_SVC_PM;  in clk_scu_get_parent()
348 	hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_PARENT;  in clk_scu_get_parent()
349 	hdr->size = 2;  in clk_scu_get_parent()
351 	msg.data.req.resource = cpu_to_le16(clk->rsrc_id);  in clk_scu_get_parent()
352 	msg.data.req.clk = clk->clk_type;  in clk_scu_get_parent()
361 	clk->parent_index = msg.data.resp.parent;  in clk_scu_get_parent()
373 	hdr->ver = IMX_SC_RPC_VERSION;  in clk_scu_set_parent()
374 	hdr->svc = IMX_SC_RPC_SVC_PM;  in clk_scu_set_parent()
375 	hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_PARENT;  in clk_scu_set_parent()
376 	hdr->size = 2;  in clk_scu_set_parent()
378 	msg.resource = cpu_to_le16(clk->rsrc_id);  in clk_scu_set_parent()
379 	msg.clk = clk->clk_type;  in clk_scu_set_parent()
389 	clk->parent_index = index;  in clk_scu_set_parent()
400 	hdr->ver = IMX_SC_RPC_VERSION;  in sc_pm_clock_enable()
401 	hdr->svc = IMX_SC_RPC_SVC_PM;  in sc_pm_clock_enable()
402 	hdr->func = IMX_SC_PM_FUNC_CLOCK_ENABLE;  in sc_pm_clock_enable()
403 	hdr->size = 3;  in sc_pm_clock_enable()
414  * clk_scu_prepare - Enable a SCU clock
423 	return sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,  in clk_scu_prepare()
424 				  clk->clk_type, true, false);  in clk_scu_prepare()
428  * clk_scu_unprepare - Disable a SCU clock
438 	ret = sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,  in clk_scu_unprepare()
439 				 clk->clk_type, false, false);  in clk_scu_unprepare()
480 		return ERR_PTR(-ENOMEM);  in __imx_clk_scu()
482 	clk->rsrc_id = rsrc_id;  in __imx_clk_scu()
483 	clk->clk_type = clk_type;  in __imx_clk_scu()
504 	clk->hw.init = &init;  in __imx_clk_scu()
506 	hw = &clk->hw;  in __imx_clk_scu()
523 	unsigned int rsrc = clkspec->args[0];  in imx_scu_of_clk_src_get()
524 	unsigned int idx = clkspec->args[1];  in imx_scu_of_clk_src_get()
528 	list_for_each_entry(clk, &scu_clks[rsrc], node) {  in imx_scu_of_clk_src_get()
529 		if (clk->clk_type == idx)  in imx_scu_of_clk_src_get()
530 			return clk->hw;  in imx_scu_of_clk_src_get()
533 	return ERR_PTR(-ENODEV);  in imx_scu_of_clk_src_get()
538 	struct device *dev = &pdev->dev;  in imx_clk_scu_probe()
543 	if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||  in imx_clk_scu_probe()
544 	    (clk->rsrc == IMX_SC_R_A72))) {  in imx_clk_scu_probe()
547 		pm_runtime_use_autosuspend(&pdev->dev);  in imx_clk_scu_probe()
558 	hw = __imx_clk_scu(dev, clk->name, clk->parents, clk->num_parents,  in imx_clk_scu_probe()
559 			   clk->rsrc, clk->clk_type);  in imx_clk_scu_probe()
565 	clk->hw = hw;  in imx_clk_scu_probe()
566 	list_add_tail(&clk->node, &imx_scu_clks[clk->rsrc]);  in imx_clk_scu_probe()
568 	if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||  in imx_clk_scu_probe()
569 	    (clk->rsrc == IMX_SC_R_A72))) {  in imx_clk_scu_probe()
570 		pm_runtime_mark_last_busy(&pdev->dev);  in imx_clk_scu_probe()
571 		pm_runtime_put_autosuspend(&pdev->dev);  in imx_clk_scu_probe()
574 	dev_dbg(dev, "register SCU clock rsrc:%d type:%d\n", clk->rsrc,  in imx_clk_scu_probe()
575 		clk->clk_type);  in imx_clk_scu_probe()
583 	u32 rsrc_id = clk->rsrc_id;  in imx_clk_scu_suspend()
589 	clk->parent = clk_hw_get_parent(&clk->hw);  in imx_clk_scu_suspend()
591 	/* DC SS needs to handle bypass clock using non-cached clock rate */  in imx_clk_scu_suspend()
592 	if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 ||  in imx_clk_scu_suspend()
593 		clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 ||  in imx_clk_scu_suspend()
594 		clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 ||  in imx_clk_scu_suspend()
595 		clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1)  in imx_clk_scu_suspend()
596 		clk->rate = clk_scu_recalc_rate(&clk->hw, 0);  in imx_clk_scu_suspend()
598 		clk->rate = clk_hw_get_rate(&clk->hw);  in imx_clk_scu_suspend()
599 	clk->is_enabled = clk_hw_is_prepared(&clk->hw);  in imx_clk_scu_suspend()
601 	if (clk->parent)  in imx_clk_scu_suspend()
602 		dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent),  in imx_clk_scu_suspend()
603 			clk->parent_index);  in imx_clk_scu_suspend()
605 	if (clk->rate)  in imx_clk_scu_suspend()
606 		dev_dbg(dev, "save rate %d\n", clk->rate);  in imx_clk_scu_suspend()
608 	if (clk->is_enabled)  in imx_clk_scu_suspend()
617 	u32 rsrc_id = clk->rsrc_id;  in imx_clk_scu_resume()
624 	if (clk->parent) {  in imx_clk_scu_resume()
625 		ret = clk_scu_set_parent(&clk->hw, clk->parent_index);  in imx_clk_scu_resume()
627 			clk_hw_get_name(clk->parent),  in imx_clk_scu_resume()
628 			clk->parent_index, !ret ? "success" : "failed");  in imx_clk_scu_resume()
631 	if (clk->rate) {  in imx_clk_scu_resume()
632 		ret = clk_scu_set_rate(&clk->hw, clk->rate, 0);  in imx_clk_scu_resume()
633 		dev_dbg(dev, "restore rate %d %s\n", clk->rate,  in imx_clk_scu_resume()
637 	if (clk->is_enabled && rsrc_id != IMX_SC_R_PI_0_PLL) {  in imx_clk_scu_resume()
638 		ret = clk_scu_prepare(&clk->hw);  in imx_clk_scu_resume()
653 		.name = "imx-scu-clk",
678 	 * A-core resources are special. SCFW reports they are not "owned" by  in imx_clk_is_resource_owned()
702 		return ERR_PTR(-EINVAL);  in imx_clk_scu_alloc_dev()
711 		return ERR_PTR(-ENOMEM);  in imx_clk_scu_alloc_dev()
718 	ret = driver_set_override(&pdev->dev, &pdev->driver_override,  in imx_clk_scu_alloc_dev()
719 				  "imx-scu-clk", strlen("imx-scu-clk"));  in imx_clk_scu_alloc_dev()
723 	ret = imx_clk_scu_attach_pd(&pdev->dev, rsrc_id);  in imx_clk_scu_alloc_dev()
746 		list_for_each_entry_safe(clk, n, &imx_scu_clks[i], node) {  in imx_clk_scu_unregister()
747 			clk_hw_unregister(clk->hw);  in imx_clk_scu_unregister()
761 	err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_div_scu_recalc_rate()
762 				      clk->gpr_id, &val);  in clk_gpr_div_scu_recalc_rate()
788 	err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_div_scu_set_rate()
789 				      clk->gpr_id, val);  in clk_gpr_div_scu_set_rate()
791 	return err ? -EINVAL : 0;  in clk_gpr_div_scu_set_rate()
805 	imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_mux_scu_get_parent()
806 				clk->gpr_id, &val);  in clk_gpr_mux_scu_get_parent()
815 	return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_mux_scu_set_parent()
816 				       clk->gpr_id, index);  in clk_gpr_mux_scu_set_parent()
829 	return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_gate_scu_prepare()
830 				       clk->gpr_id, !clk->gate_invert);  in clk_gpr_gate_scu_prepare()
838 	ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_gate_scu_unprepare()
839 				      clk->gpr_id, clk->gate_invert);  in clk_gpr_gate_scu_unprepare()
851 	ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,  in clk_gpr_gate_scu_is_prepared()
852 				      clk->gpr_id, &val);  in clk_gpr_gate_scu_is_prepared()
856 	return clk->gate_invert ? !val : val;  in clk_gpr_gate_scu_is_prepared()
876 		return ERR_PTR(-EINVAL);  in __imx_clk_gpr_scu()
880 		return ERR_PTR(-ENOMEM);  in __imx_clk_gpr_scu()
884 		return ERR_PTR(-EINVAL);  in __imx_clk_gpr_scu()
895 		return ERR_PTR(-ENOMEM);  in __imx_clk_gpr_scu()
898 	clk->rsrc_id = rsrc_id;  in __imx_clk_gpr_scu()
899 	clk->gpr_id = gpr_id;  in __imx_clk_gpr_scu()
900 	clk->flags = flags;  in __imx_clk_gpr_scu()
901 	clk->gate_invert = invert;  in __imx_clk_gpr_scu()
917 	clk->hw.init = &init;  in __imx_clk_gpr_scu()
919 	hw = &clk->hw;  in __imx_clk_gpr_scu()
926 		clk_node->hw = hw;  in __imx_clk_gpr_scu()
927 		clk_node->clk_type = gpr_id;  in __imx_clk_gpr_scu()
928 		list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]);  in __imx_clk_gpr_scu()