Lines Matching +full:pll +full:-
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
33 * struct clk_pllv3 - IMX PLL clock version 3
35 * @base: base address of PLL registers
36 * @power_bit: pll power bit mask
37 * @powerup_set: set power_bit to power up the PLL
44 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
61 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
63 u32 val = readl_relaxed(pll->base) & pll->power_bit;
65 /* No need to wait for lock when pll is not powered up */
66 if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
69 return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK,
75 struct clk_pllv3 *pll = to_clk_pllv3(hw);
78 val = readl_relaxed(pll->base);
79 if (pll->powerup_set)
80 val |= pll->power_bit;
82 val &= ~pll->power_bit;
83 writel_relaxed(val, pll->base);
85 return clk_pllv3_wait_lock(pll);
90 struct clk_pllv3 *pll = to_clk_pllv3(hw);
93 val = readl_relaxed(pll->base);
94 if (pll->powerup_set)
95 val &= ~pll->power_bit;
97 val |= pll->power_bit;
98 writel_relaxed(val, pll->base);
103 struct clk_pllv3 *pll = to_clk_pllv3(hw);
105 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
114 struct clk_pllv3 *pll = to_clk_pllv3(hw);
115 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
123 unsigned long parent_rate = req->best_parent_rate;
125 req->rate = (req->rate >= parent_rate * 22) ? parent_rate * 22 : parent_rate * 20;
133 struct clk_pllv3 *pll = to_clk_pllv3(hw);
141 return -EINVAL;
143 val = readl_relaxed(pll->base);
144 val &= ~(pll->div_mask << pll->div_shift);
145 val |= (div << pll->div_shift);
146 writel_relaxed(val, pll->base);
148 return clk_pllv3_wait_lock(pll);
163 struct clk_pllv3 *pll = to_clk_pllv3(hw);
164 u32 div = readl_relaxed(pll->base) & pll->div_mask;
172 unsigned long parent_rate = req->best_parent_rate;
177 if (req->rate > max_rate)
178 req->rate = max_rate;
179 else if (req->rate < min_rate)
180 req->rate = min_rate;
181 div = req->rate * 2 / parent_rate;
183 req->rate = parent_rate * div / 2;
191 struct clk_pllv3 *pll = to_clk_pllv3(hw);
197 return -EINVAL;
200 val = readl_relaxed(pll->base);
201 val &= ~pll->div_mask;
203 writel_relaxed(val, pll->base);
205 return clk_pllv3_wait_lock(pll);
220 struct clk_pllv3 *pll = to_clk_pllv3(hw);
221 u32 mfn = readl_relaxed(pll->base + pll->num_offset);
222 u32 mfd = readl_relaxed(pll->base + pll->denom_offset);
223 u32 div = readl_relaxed(pll->base) & pll->div_mask;
235 unsigned long parent_rate = req->best_parent_rate;
243 if (req->rate > max_rate)
244 req->rate = max_rate;
245 else if (req->rate < min_rate)
246 req->rate = min_rate;
251 div = req->rate / parent_rate;
252 temp64 = (u64) (req->rate - div * parent_rate);
261 req->rate = parent_rate * div + (unsigned long)temp64;
269 struct clk_pllv3 *pll = to_clk_pllv3(hw);
278 return -EINVAL;
284 temp64 = (u64) (rate - div * parent_rate);
289 val = readl_relaxed(pll->base);
290 val &= ~pll->div_mask;
292 writel_relaxed(val, pll->base);
293 writel_relaxed(mfn, pll->base + pll->num_offset);
294 writel_relaxed(mfd, pll->base + pll->denom_offset);
296 return clk_pllv3_wait_lock(pll);
310 u32 mfn; /* numerator, 30-bit value */
311 u32 mfd; /* denominator, 30-bit value, must be less than mfn */
338 mf.mfn = mf.mfd - 1;
341 temp64 = rate - parent_rate * mf.mfi;
353 struct clk_pllv3 *pll = to_clk_pllv3(hw);
356 mf.mfn = readl_relaxed(pll->base + pll->num_offset);
357 mf.mfd = readl_relaxed(pll->base + pll->denom_offset);
358 mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
366 struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(req->best_parent_rate,
367 req->rate);
369 req->rate = clk_pllv3_vf610_mf_to_rate(req->best_parent_rate, mf);
377 struct clk_pllv3 *pll = to_clk_pllv3(hw);
382 val = readl_relaxed(pll->base);
384 val &= ~pll->div_mask; /* clear bit for mfi=20 */
386 val |= pll->div_mask; /* set bit for mfi=22 */
387 writel_relaxed(val, pll->base);
389 writel_relaxed(mf.mfn, pll->base + pll->num_offset);
390 writel_relaxed(mf.mfd, pll->base + pll->denom_offset);
392 return clk_pllv3_wait_lock(pll);
407 struct clk_pllv3 *pll = to_clk_pllv3(hw);
409 return pll->ref_clock;
423 struct clk_pllv3 *pll;
429 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
430 if (!pll)
431 return ERR_PTR(-ENOMEM);
433 pll->power_bit = BM_PLL_POWER;
434 pll->num_offset = PLL_NUM_OFFSET;
435 pll->denom_offset = PLL_DENOM_OFFSET;
443 pll->num_offset = PLL_VF610_NUM_OFFSET;
444 pll->denom_offset = PLL_VF610_DENOM_OFFSET;
447 pll->div_shift = 1;
451 pll->powerup_set = true;
454 pll->num_offset = PLL_IMX7_NUM_OFFSET;
455 pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
461 pll->power_bit = IMX7_ENET_PLL_POWER;
462 pll->ref_clock = 1000000000;
466 pll->ref_clock = 500000000;
470 pll->power_bit = IMX7_DDR_PLL_POWER;
471 pll->num_offset = PLL_IMX7_NUM_OFFSET;
472 pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
478 pll->base = base;
479 pll->div_mask = div_mask;
487 pll->hw.init = &init;
488 hw = &pll->hw;
492 kfree(pll);