Lines Matching full:rate

94 		struct clk_pll14xx *pll, unsigned long rate)
100 if (rate == rate_table[i].rate)
121 unsigned long rate, unsigned long prate)
125 /* calc kdiv = round(rate * pdiv * 65536 * 2^sdiv / prate) - (mdiv * 65536) */
126 kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536);
131 static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rate,
151 /* First try if we can get the desired rate from one of the static entries */
152 tt = imx_get_pll_settings(pll, rate);
155 clk_hw_get_name(&pll->hw), prate, rate);
156 t->rate = tt->rate;
170 /* Then see if we can get the desired rate by only adjusting kdiv (glitch free) */
174 if (rate >= rate_min && rate <= rate_max) {
175 kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate);
177 clk_hw_get_name(&pll->hw), prate, rate,
180 t->rate = (unsigned int)fout;
191 /* calc mdiv = round(rate * pdiv * 2^sdiv) / prate) */
192 mdiv = DIV_ROUND_CLOSEST(rate * (pdiv << sdiv), prate);
195 kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate);
199 dist = abs((long)rate - (long)fout);
202 t->rate = (unsigned int)fout;
215 clk_hw_get_name(&pll->hw), prate, rate, t->rate, t->pdiv, t->sdiv,
228 if (req->rate >= rate_table[i].rate) {
229 req->rate = rate_table[i].rate;
235 req->rate = rate_table[pll->rate_count - 1].rate;
246 imx_pll14xx_calc_settings(pll, req->rate, req->best_parent_rate, &t);
248 req->rate = t.rate;
274 static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate,
282 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
297 const struct imx_pll14xx_rate_table *rate;
301 rate = imx_get_pll_settings(pll, drate);
302 if (!rate) {
303 pr_err("Invalid rate %lu for pll clk %s\n", drate,
310 if (!clk_pll14xx_mp_change(rate, tmp)) {
312 tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv);
331 div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | FIELD_PREP(PDIV_MASK, rate->pdiv) |
332 FIELD_PREP(SDIV_MASK, rate->sdiv);
363 struct imx_pll14xx_rate_table rate;
367 imx_pll14xx_calc_settings(pll, drate, prate, &rate);
371 if (!clk_pll14xx_mp_change(&rate, div_ctl0)) {
374 div_ctl0 |= FIELD_PREP(SDIV_MASK, rate.sdiv);
377 writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv),
392 div_ctl0 = FIELD_PREP(MDIV_MASK, rate.mdiv) |
393 FIELD_PREP(PDIV_MASK, rate.pdiv) |
394 FIELD_PREP(SDIV_MASK, rate.sdiv);
397 writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1);