353 	struct imx95_blk_ctl *bc;  in imx95_bc_probe()  local
359 	bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);  in imx95_bc_probe()
360 	if (!bc)  in imx95_bc_probe()
362 	bc->dev = dev;  in imx95_bc_probe()
363 	dev_set_drvdata(&pdev->dev, bc);  in imx95_bc_probe()
365 	spin_lock_init(&bc->lock);  in imx95_bc_probe()
371 	bc->base = base;  in imx95_bc_probe()
372 	bc->clk_apb = devm_clk_get(dev, NULL);  in imx95_bc_probe()
373 	if (IS_ERR(bc->clk_apb))  in imx95_bc_probe()
374 		return dev_err_probe(dev, PTR_ERR(bc->clk_apb), "failed to get APB clock\n");  in imx95_bc_probe()
376 	ret = clk_prepare_enable(bc->clk_apb);  in imx95_bc_probe()
382 	bc->pdata = of_device_get_match_data(dev);  in imx95_bc_probe()
383 	if (!bc->pdata)  in imx95_bc_probe()
386 	clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, bc->pdata->num_clks),  in imx95_bc_probe()
391 	if (bc->pdata->rpm_enabled) {  in imx95_bc_probe()
396 	clk_hw_data->num = bc->pdata->num_clks;  in imx95_bc_probe()
399 	for (i = 0; i < bc->pdata->num_clks; i++) {  in imx95_bc_probe()
400 		const struct imx95_blk_ctl_clk_dev_data *data = &bc->pdata->clk_dev_data[i];  in imx95_bc_probe()
407 						     data->flags2, &bc->lock);  in imx95_bc_probe()
411 							 data->bit_width, data->flags2, &bc->lock);  in imx95_bc_probe()
415 						      data->flags2, &bc->lock);  in imx95_bc_probe()
434 	if (pm_runtime_enabled(bc->dev)) {  in imx95_bc_probe()
436 		clk_disable_unprepare(bc->clk_apb);  in imx95_bc_probe()
442 	for (i = 0; i < bc->pdata->num_clks; i++) {  in imx95_bc_probe()
454 	struct imx95_blk_ctl *bc = dev_get_drvdata(dev);  in imx95_bc_runtime_suspend()  local
456 	bc->clk_reg_restore = readl(bc->base + bc->pdata->clk_reg_offset);  in imx95_bc_runtime_suspend()
457 	clk_disable_unprepare(bc->clk_apb);  in imx95_bc_runtime_suspend()
464 	struct imx95_blk_ctl *bc = dev_get_drvdata(dev);  in imx95_bc_runtime_resume()  local
467 	ret = clk_prepare_enable(bc->clk_apb);  in imx95_bc_runtime_resume()
471 	writel(bc->clk_reg_restore, bc->base + bc->pdata->clk_reg_offset);  in imx95_bc_runtime_resume()
480 	struct imx95_blk_ctl *bc = dev_get_drvdata(dev);  in imx95_bc_suspend()  local
485 	bc->clk_reg_restore = readl(bc->base + bc->pdata->clk_reg_offset);  in imx95_bc_suspend()
486 	clk_disable_unprepare(bc->clk_apb);  in imx95_bc_suspend()
493 	struct imx95_blk_ctl *bc = dev_get_drvdata(dev);  in imx95_bc_resume()  local
499 	ret = clk_prepare_enable(bc->clk_apb);  in imx95_bc_resume()
503 	writel(bc->clk_reg_restore, bc->base + bc->pdata->clk_reg_offset);  in imx95_bc_resume()