1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright 2024-2025 NXP
6 #include <dt-bindings/clock/nxp,imx94-clock.h>
7 #include <dt-bindings/clock/nxp,imx95-clock.h>
9 #include <linux/clk-provider.h>
352 	struct device *dev = &pdev->dev;  in imx95_bc_probe()
361 		return -ENOMEM;  in imx95_bc_probe()
362 	bc->dev = dev;  in imx95_bc_probe()
363 	dev_set_drvdata(&pdev->dev, bc);  in imx95_bc_probe()
365 	spin_lock_init(&bc->lock);  in imx95_bc_probe()
371 	bc->base = base;  in imx95_bc_probe()
372 	bc->clk_apb = devm_clk_get(dev, NULL);  in imx95_bc_probe()
373 	if (IS_ERR(bc->clk_apb))  in imx95_bc_probe()
374 		return dev_err_probe(dev, PTR_ERR(bc->clk_apb), "failed to get APB clock\n");  in imx95_bc_probe()
376 	ret = clk_prepare_enable(bc->clk_apb);  in imx95_bc_probe()
382 	bc->pdata = of_device_get_match_data(dev);  in imx95_bc_probe()
383 	if (!bc->pdata)  in imx95_bc_probe()
386 	clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, bc->pdata->num_clks),  in imx95_bc_probe()
389 		return -ENOMEM;  in imx95_bc_probe()
391 	if (bc->pdata->rpm_enabled) {  in imx95_bc_probe()
392 		devm_pm_runtime_enable(&pdev->dev);  in imx95_bc_probe()
393 		pm_runtime_resume_and_get(&pdev->dev);  in imx95_bc_probe()
396 	clk_hw_data->num = bc->pdata->num_clks;  in imx95_bc_probe()
397 	hws = clk_hw_data->hws;  in imx95_bc_probe()
399 	for (i = 0; i < bc->pdata->num_clks; i++) {  in imx95_bc_probe()
400 		const struct imx95_blk_ctl_clk_dev_data *data = &bc->pdata->clk_dev_data[i];  in imx95_bc_probe()
401 		void __iomem *reg = base + data->reg;  in imx95_bc_probe()
403 		if (data->type == CLK_MUX) {  in imx95_bc_probe()
404 			hws[i] = clk_hw_register_mux(dev, data->name, data->parent_names,  in imx95_bc_probe()
405 						     data->num_parents, data->flags, reg,  in imx95_bc_probe()
406 						     data->bit_idx, data->bit_width,  in imx95_bc_probe()
407 						     data->flags2, &bc->lock);  in imx95_bc_probe()
408 		} else if (data->type == CLK_DIVIDER) {  in imx95_bc_probe()
409 			hws[i] = clk_hw_register_divider(dev, data->name, data->parent_names[0],  in imx95_bc_probe()
410 							 data->flags, reg, data->bit_idx,  in imx95_bc_probe()
411 							 data->bit_width, data->flags2, &bc->lock);  in imx95_bc_probe()
413 			hws[i] = clk_hw_register_gate(dev, data->name, data->parent_names[0],  in imx95_bc_probe()
414 						      data->flags, reg, data->bit_idx,  in imx95_bc_probe()
415 						      data->flags2, &bc->lock);  in imx95_bc_probe()
419 			dev_err(dev, "failed to register: %s:%d\n", data->name, ret);  in imx95_bc_probe()
424 	ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, clk_hw_data);  in imx95_bc_probe()
430 		of_clk_del_provider(dev->of_node);  in imx95_bc_probe()
434 	if (pm_runtime_enabled(bc->dev)) {  in imx95_bc_probe()
435 		pm_runtime_put_sync(&pdev->dev);  in imx95_bc_probe()
436 		clk_disable_unprepare(bc->clk_apb);  in imx95_bc_probe()
442 	for (i = 0; i < bc->pdata->num_clks; i++) {  in imx95_bc_probe()
456 	bc->clk_reg_restore = readl(bc->base + bc->pdata->clk_reg_offset);  in imx95_bc_runtime_suspend()
457 	clk_disable_unprepare(bc->clk_apb);  in imx95_bc_runtime_suspend()
467 	ret = clk_prepare_enable(bc->clk_apb);  in imx95_bc_runtime_resume()
471 	writel(bc->clk_reg_restore, bc->base + bc->pdata->clk_reg_offset);  in imx95_bc_runtime_resume()
485 	bc->clk_reg_restore = readl(bc->base + bc->pdata->clk_reg_offset);  in imx95_bc_suspend()
486 	clk_disable_unprepare(bc->clk_apb);  in imx95_bc_suspend()
499 	ret = clk_prepare_enable(bc->clk_apb);  in imx95_bc_resume()
503 	writel(bc->clk_reg_restore, bc->base + bc->pdata->clk_reg_offset);  in imx95_bc_resume()
515 	{ .compatible = "nxp,imx94-display-csr", .data = &imx94_dispmix_csr_dev_data },
516 	{ .compatible = "nxp,imx94-lvds-csr", .data = &imx94_lvds_csr_dev_data },
517 	{ .compatible = "nxp,imx95-camera-csr", .data = &camblk_dev_data },
518 	{ .compatible = "nxp,imx95-display-master-csr", },
519 	{ .compatible = "nxp,imx95-display-csr", .data = &imx95_dispmix_csr_dev_data },
520 	{ .compatible = "nxp,imx95-lvds-csr", .data = &imx95_lvds_csr_dev_data },
521 	{ .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data },
522 	{ .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
523 	{ .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
531 		.name = "imx95-blk-ctl",
538 MODULE_DESCRIPTION("NXP i.MX95 blk ctl driver");