Lines Matching +full:- +full:30
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8ulp-clock.h>
12 #include <linux/reset-controller.h>
85 u32 offset = pcc_reset->resets[id]; in imx8ulp_pcc_assert()
89 spin_lock_irqsave(pcc_reset->lock, flags); in imx8ulp_pcc_assert()
91 val = readl(pcc_reset->base + offset); in imx8ulp_pcc_assert()
93 writel(val, pcc_reset->base + offset); in imx8ulp_pcc_assert()
95 spin_unlock_irqrestore(pcc_reset->lock, flags); in imx8ulp_pcc_assert()
103 u32 offset = pcc_reset->resets[id]; in imx8ulp_pcc_deassert()
107 spin_lock_irqsave(pcc_reset->lock, flags); in imx8ulp_pcc_deassert()
109 val = readl(pcc_reset->base + offset); in imx8ulp_pcc_deassert()
111 writel(val, pcc_reset->base + offset); in imx8ulp_pcc_deassert()
113 spin_unlock_irqrestore(pcc_reset->lock, flags); in imx8ulp_pcc_deassert()
126 struct device_node *np = pdev->dev.of_node; in imx8ulp_pcc_reset_init()
127 struct device *dev = &pdev->dev; in imx8ulp_pcc_reset_init()
132 return -ENOMEM; in imx8ulp_pcc_reset_init()
134 pcc_reset->base = base; in imx8ulp_pcc_reset_init()
135 pcc_reset->lock = &imx_ccm_lock; in imx8ulp_pcc_reset_init()
136 pcc_reset->resets = resets; in imx8ulp_pcc_reset_init()
137 pcc_reset->rcdev.owner = THIS_MODULE; in imx8ulp_pcc_reset_init()
138 pcc_reset->rcdev.nr_resets = nr_resets; in imx8ulp_pcc_reset_init()
139 pcc_reset->rcdev.ops = &imx8ulp_pcc_reset_ops; in imx8ulp_pcc_reset_init()
140 pcc_reset->rcdev.of_node = np; in imx8ulp_pcc_reset_init()
142 return devm_reset_controller_register(dev, &pcc_reset->rcdev); in imx8ulp_pcc_reset_init()
147 struct device *dev = &pdev->dev; in imx8ulp_clk_cgc1_init()
155 return -ENOMEM; in imx8ulp_clk_cgc1_init()
157 clk_data->num = IMX8ULP_CLK_CGC1_END; in imx8ulp_clk_cgc1_init()
158 clks = clk_data->hws; in imx8ulp_clk_cgc1_init()
224 imx_check_clk_hws(clks, clk_data->num); in imx8ulp_clk_cgc1_init()
231 struct device *dev = &pdev->dev; in imx8ulp_clk_cgc2_init()
239 return -ENOMEM; in imx8ulp_clk_cgc2_init()
241 clk_data->num = IMX8ULP_CLK_CGC2_END; in imx8ulp_clk_cgc2_init()
242 clks = clk_data->hws; in imx8ulp_clk_cgc2_init()
306 imx_check_clk_hws(clks, clk_data->num); in imx8ulp_clk_cgc2_init()
313 struct device *dev = &pdev->dev; in imx8ulp_clk_pcc3_init()
322 return -ENOMEM; in imx8ulp_clk_pcc3_init()
324 clk_data->num = IMX8ULP_CLK_PCC3_END; in imx8ulp_clk_pcc3_init()
325 clks = clk_data->hws; in imx8ulp_clk_pcc3_init()
345 clks[IMX8ULP_CLK_DMA1_MP] = imx_clk_hw_gate("pcc_dma1_mp", "xbar_ad_divplat", base + 0x4, 30); in imx8ulp_clk_pcc3_init()
346 clks[IMX8ULP_CLK_DMA1_CH0] = imx_clk_hw_gate("pcc_dma1_ch0", "xbar_ad_divplat", base + 0x8, 30); in imx8ulp_clk_pcc3_init()
347 clks[IMX8ULP_CLK_DMA1_CH1] = imx_clk_hw_gate("pcc_dma1_ch1", "xbar_ad_divplat", base + 0xc, 30); in imx8ulp_clk_pcc3_init()
348 clks[IMX8ULP_CLK_DMA1_CH2] = imx_clk_hw_gate("pcc_dma1_ch2", "xbar_ad_divplat", base + 0x10, 30); in imx8ulp_clk_pcc3_init()
349 clks[IMX8ULP_CLK_DMA1_CH3] = imx_clk_hw_gate("pcc_dma1_ch3", "xbar_ad_divplat", base + 0x14, 30); in imx8ulp_clk_pcc3_init()
350 clks[IMX8ULP_CLK_DMA1_CH4] = imx_clk_hw_gate("pcc_dma1_ch4", "xbar_ad_divplat", base + 0x18, 30); in imx8ulp_clk_pcc3_init()
351 clks[IMX8ULP_CLK_DMA1_CH5] = imx_clk_hw_gate("pcc_dma1_ch5", "xbar_ad_divplat", base + 0x1c, 30); in imx8ulp_clk_pcc3_init()
352 clks[IMX8ULP_CLK_DMA1_CH6] = imx_clk_hw_gate("pcc_dma1_ch6", "xbar_ad_divplat", base + 0x20, 30); in imx8ulp_clk_pcc3_init()
353 clks[IMX8ULP_CLK_DMA1_CH7] = imx_clk_hw_gate("pcc_dma1_ch7", "xbar_ad_divplat", base + 0x24, 30); in imx8ulp_clk_pcc3_init()
354 clks[IMX8ULP_CLK_DMA1_CH8] = imx_clk_hw_gate("pcc_dma1_ch8", "xbar_ad_divplat", base + 0x28, 30); in imx8ulp_clk_pcc3_init()
355 clks[IMX8ULP_CLK_DMA1_CH9] = imx_clk_hw_gate("pcc_dma1_ch9", "xbar_ad_divplat", base + 0x2c, 30); in imx8ulp_clk_pcc3_init()
356 clks[IMX8ULP_CLK_DMA1_CH10] = imx_clk_hw_gate("pcc_dma1_ch10", "xbar_ad_divplat", base + 0x30, 30); in imx8ulp_clk_pcc3_init()
357 clks[IMX8ULP_CLK_DMA1_CH11] = imx_clk_hw_gate("pcc_dma1_ch11", "xbar_ad_divplat", base + 0x34, 30); in imx8ulp_clk_pcc3_init()
358 clks[IMX8ULP_CLK_DMA1_CH12] = imx_clk_hw_gate("pcc_dma1_ch12", "xbar_ad_divplat", base + 0x38, 30); in imx8ulp_clk_pcc3_init()
359 clks[IMX8ULP_CLK_DMA1_CH13] = imx_clk_hw_gate("pcc_dma1_ch13", "xbar_ad_divplat", base + 0x3c, 30); in imx8ulp_clk_pcc3_init()
360 clks[IMX8ULP_CLK_DMA1_CH14] = imx_clk_hw_gate("pcc_dma1_ch14", "xbar_ad_divplat", base + 0x40, 30); in imx8ulp_clk_pcc3_init()
361 clks[IMX8ULP_CLK_DMA1_CH15] = imx_clk_hw_gate("pcc_dma1_ch15", "xbar_ad_divplat", base + 0x44, 30); in imx8ulp_clk_pcc3_init()
362 clks[IMX8ULP_CLK_DMA1_CH16] = imx_clk_hw_gate("pcc_dma1_ch16", "xbar_ad_divplat", base + 0x48, 30); in imx8ulp_clk_pcc3_init()
363 clks[IMX8ULP_CLK_DMA1_CH17] = imx_clk_hw_gate("pcc_dma1_ch17", "xbar_ad_divplat", base + 0x4c, 30); in imx8ulp_clk_pcc3_init()
364 clks[IMX8ULP_CLK_DMA1_CH18] = imx_clk_hw_gate("pcc_dma1_ch18", "xbar_ad_divplat", base + 0x50, 30); in imx8ulp_clk_pcc3_init()
365 clks[IMX8ULP_CLK_DMA1_CH19] = imx_clk_hw_gate("pcc_dma1_ch19", "xbar_ad_divplat", base + 0x54, 30); in imx8ulp_clk_pcc3_init()
366 clks[IMX8ULP_CLK_DMA1_CH20] = imx_clk_hw_gate("pcc_dma1_ch20", "xbar_ad_divplat", base + 0x58, 30); in imx8ulp_clk_pcc3_init()
367 clks[IMX8ULP_CLK_DMA1_CH21] = imx_clk_hw_gate("pcc_dma1_ch21", "xbar_ad_divplat", base + 0x5c, 30); in imx8ulp_clk_pcc3_init()
368 clks[IMX8ULP_CLK_DMA1_CH22] = imx_clk_hw_gate("pcc_dma1_ch22", "xbar_ad_divplat", base + 0x60, 30); in imx8ulp_clk_pcc3_init()
369 clks[IMX8ULP_CLK_DMA1_CH23] = imx_clk_hw_gate("pcc_dma1_ch23", "xbar_ad_divplat", base + 0x64, 30); in imx8ulp_clk_pcc3_init()
370 clks[IMX8ULP_CLK_DMA1_CH24] = imx_clk_hw_gate("pcc_dma1_ch24", "xbar_ad_divplat", base + 0x68, 30); in imx8ulp_clk_pcc3_init()
371 clks[IMX8ULP_CLK_DMA1_CH25] = imx_clk_hw_gate("pcc_dma1_ch25", "xbar_ad_divplat", base + 0x6c, 30); in imx8ulp_clk_pcc3_init()
372 clks[IMX8ULP_CLK_DMA1_CH26] = imx_clk_hw_gate("pcc_dma1_ch26", "xbar_ad_divplat", base + 0x70, 30); in imx8ulp_clk_pcc3_init()
373 clks[IMX8ULP_CLK_DMA1_CH27] = imx_clk_hw_gate("pcc_dma1_ch27", "xbar_ad_divplat", base + 0x74, 30); in imx8ulp_clk_pcc3_init()
374 clks[IMX8ULP_CLK_DMA1_CH28] = imx_clk_hw_gate("pcc_dma1_ch28", "xbar_ad_divplat", base + 0x78, 30); in imx8ulp_clk_pcc3_init()
375 clks[IMX8ULP_CLK_DMA1_CH29] = imx_clk_hw_gate("pcc_dma1_ch29", "xbar_ad_divplat", base + 0x7c, 30); in imx8ulp_clk_pcc3_init()
376 clks[IMX8ULP_CLK_DMA1_CH30] = imx_clk_hw_gate("pcc_dma1_ch30", "xbar_ad_divplat", base + 0x80, 30); in imx8ulp_clk_pcc3_init()
377 clks[IMX8ULP_CLK_DMA1_CH31] = imx_clk_hw_gate("pcc_dma1_ch31", "xbar_ad_divplat", base + 0x84, 30); in imx8ulp_clk_pcc3_init()
378 …clks[IMX8ULP_CLK_MU0_B] = imx_clk_hw_gate_flags("mu0_b", "xbar_ad_divplat", base + 0x88, 30, CLK_I… in imx8ulp_clk_pcc3_init()
379 clks[IMX8ULP_CLK_MU3_A] = imx_clk_hw_gate("mu3_a", "xbar_ad_divplat", base + 0x8c, 30); in imx8ulp_clk_pcc3_init()
380 …clks[IMX8ULP_CLK_TPM5] = imx_clk_hw_gate_flags("tpm5", "sosc_div2", base + 0xd0, 30, CLK_IS_CRITI… in imx8ulp_clk_pcc3_init()
382 imx_check_clk_hws(clks, clk_data->num); in imx8ulp_clk_pcc3_init()
396 struct device *dev = &pdev->dev; in imx8ulp_clk_pcc4_init()
405 return -ENOMEM; in imx8ulp_clk_pcc4_init()
407 clk_data->num = IMX8ULP_CLK_PCC4_END; in imx8ulp_clk_pcc4_init()
408 clks = clk_data->hws; in imx8ulp_clk_pcc4_init()
424 clks[IMX8ULP_CLK_PCTLE] = imx_clk_hw_gate("pctle", "xbar_divbus", base + 0x28, 30); in imx8ulp_clk_pcc4_init()
425 clks[IMX8ULP_CLK_PCTLF] = imx_clk_hw_gate("pctlf", "xbar_divbus", base + 0x2c, 30); in imx8ulp_clk_pcc4_init()
433 clks[IMX8ULP_CLK_USB_XBAR] = imx_clk_hw_gate("usb_xbar", "xbar_divbus", base + 0x50, 30); in imx8ulp_clk_pcc4_init()
435 clks[IMX8ULP_CLK_RGPIOE] = imx_clk_hw_gate("rgpioe", "nic_per_divplat", base + 0x78, 30); in imx8ulp_clk_pcc4_init()
436 clks[IMX8ULP_CLK_RGPIOF] = imx_clk_hw_gate("rgpiof", "nic_per_divplat", base + 0x7c, 30); in imx8ulp_clk_pcc4_init()
438 imx_check_clk_hws(clks, clk_data->num); in imx8ulp_clk_pcc4_init()
451 struct device *dev = &pdev->dev; in imx8ulp_clk_pcc5_init()
460 return -ENOMEM; in imx8ulp_clk_pcc5_init()
462 clk_data->num = IMX8ULP_CLK_PCC5_END; in imx8ulp_clk_pcc5_init()
463 clks = clk_data->hws; in imx8ulp_clk_pcc5_init()
470 clks[IMX8ULP_CLK_DMA2_MP] = imx_clk_hw_gate("pcc_dma2_mp", "lpav_axi_div", base + 0x0, 30); in imx8ulp_clk_pcc5_init()
471 clks[IMX8ULP_CLK_DMA2_CH0] = imx_clk_hw_gate("pcc_dma2_ch0", "lpav_axi_div", base + 0x4, 30); in imx8ulp_clk_pcc5_init()
472 clks[IMX8ULP_CLK_DMA2_CH1] = imx_clk_hw_gate("pcc_dma2_ch1", "lpav_axi_div", base + 0x8, 30); in imx8ulp_clk_pcc5_init()
473 clks[IMX8ULP_CLK_DMA2_CH2] = imx_clk_hw_gate("pcc_dma2_ch2", "lpav_axi_div", base + 0xc, 30); in imx8ulp_clk_pcc5_init()
474 clks[IMX8ULP_CLK_DMA2_CH3] = imx_clk_hw_gate("pcc_dma2_ch3", "lpav_axi_div", base + 0x10, 30); in imx8ulp_clk_pcc5_init()
475 clks[IMX8ULP_CLK_DMA2_CH4] = imx_clk_hw_gate("pcc_dma2_ch4", "lpav_axi_div", base + 0x14, 30); in imx8ulp_clk_pcc5_init()
476 clks[IMX8ULP_CLK_DMA2_CH5] = imx_clk_hw_gate("pcc_dma2_ch5", "lpav_axi_div", base + 0x18, 30); in imx8ulp_clk_pcc5_init()
477 clks[IMX8ULP_CLK_DMA2_CH6] = imx_clk_hw_gate("pcc_dma2_ch6", "lpav_axi_div", base + 0x1c, 30); in imx8ulp_clk_pcc5_init()
478 clks[IMX8ULP_CLK_DMA2_CH7] = imx_clk_hw_gate("pcc_dma2_ch7", "lpav_axi_div", base + 0x20, 30); in imx8ulp_clk_pcc5_init()
479 clks[IMX8ULP_CLK_DMA2_CH8] = imx_clk_hw_gate("pcc_dma2_ch8", "lpav_axi_div", base + 0x24, 30); in imx8ulp_clk_pcc5_init()
480 clks[IMX8ULP_CLK_DMA2_CH9] = imx_clk_hw_gate("pcc_dma2_ch9", "lpav_axi_div", base + 0x28, 30); in imx8ulp_clk_pcc5_init()
481 clks[IMX8ULP_CLK_DMA2_CH10] = imx_clk_hw_gate("pcc_dma2_ch10", "lpav_axi_div", base + 0x2c, 30); in imx8ulp_clk_pcc5_init()
482 clks[IMX8ULP_CLK_DMA2_CH11] = imx_clk_hw_gate("pcc_dma2_ch11", "lpav_axi_div", base + 0x30, 30); in imx8ulp_clk_pcc5_init()
483 clks[IMX8ULP_CLK_DMA2_CH12] = imx_clk_hw_gate("pcc_dma2_ch12", "lpav_axi_div", base + 0x34, 30); in imx8ulp_clk_pcc5_init()
484 clks[IMX8ULP_CLK_DMA2_CH13] = imx_clk_hw_gate("pcc_dma2_ch13", "lpav_axi_div", base + 0x38, 30); in imx8ulp_clk_pcc5_init()
485 clks[IMX8ULP_CLK_DMA2_CH14] = imx_clk_hw_gate("pcc_dma2_ch14", "lpav_axi_div", base + 0x3c, 30); in imx8ulp_clk_pcc5_init()
486 clks[IMX8ULP_CLK_DMA2_CH15] = imx_clk_hw_gate("pcc_dma2_ch15", "lpav_axi_div", base + 0x40, 30); in imx8ulp_clk_pcc5_init()
487 clks[IMX8ULP_CLK_DMA2_CH16] = imx_clk_hw_gate("pcc_dma2_ch16", "lpav_axi_div", base + 0x44, 30); in imx8ulp_clk_pcc5_init()
488 clks[IMX8ULP_CLK_DMA2_CH17] = imx_clk_hw_gate("pcc_dma2_ch17", "lpav_axi_div", base + 0x48, 30); in imx8ulp_clk_pcc5_init()
489 clks[IMX8ULP_CLK_DMA2_CH18] = imx_clk_hw_gate("pcc_dma2_ch18", "lpav_axi_div", base + 0x4c, 30); in imx8ulp_clk_pcc5_init()
490 clks[IMX8ULP_CLK_DMA2_CH19] = imx_clk_hw_gate("pcc_dma2_ch19", "lpav_axi_div", base + 0x50, 30); in imx8ulp_clk_pcc5_init()
491 clks[IMX8ULP_CLK_DMA2_CH20] = imx_clk_hw_gate("pcc_dma2_ch20", "lpav_axi_div", base + 0x54, 30); in imx8ulp_clk_pcc5_init()
492 clks[IMX8ULP_CLK_DMA2_CH21] = imx_clk_hw_gate("pcc_dma2_ch21", "lpav_axi_div", base + 0x58, 30); in imx8ulp_clk_pcc5_init()
493 clks[IMX8ULP_CLK_DMA2_CH22] = imx_clk_hw_gate("pcc_dma2_ch22", "lpav_axi_div", base + 0x5c, 30); in imx8ulp_clk_pcc5_init()
494 clks[IMX8ULP_CLK_DMA2_CH23] = imx_clk_hw_gate("pcc_dma2_ch23", "lpav_axi_div", base + 0x60, 30); in imx8ulp_clk_pcc5_init()
495 clks[IMX8ULP_CLK_DMA2_CH24] = imx_clk_hw_gate("pcc_dma2_ch24", "lpav_axi_div", base + 0x64, 30); in imx8ulp_clk_pcc5_init()
496 clks[IMX8ULP_CLK_DMA2_CH25] = imx_clk_hw_gate("pcc_dma2_ch25", "lpav_axi_div", base + 0x68, 30); in imx8ulp_clk_pcc5_init()
497 clks[IMX8ULP_CLK_DMA2_CH26] = imx_clk_hw_gate("pcc_dma2_ch26", "lpav_axi_div", base + 0x6c, 30); in imx8ulp_clk_pcc5_init()
498 clks[IMX8ULP_CLK_DMA2_CH27] = imx_clk_hw_gate("pcc_dma2_ch27", "lpav_axi_div", base + 0x70, 30); in imx8ulp_clk_pcc5_init()
499 clks[IMX8ULP_CLK_DMA2_CH28] = imx_clk_hw_gate("pcc_dma2_ch28", "lpav_axi_div", base + 0x74, 30); in imx8ulp_clk_pcc5_init()
500 clks[IMX8ULP_CLK_DMA2_CH29] = imx_clk_hw_gate("pcc_dma2_ch29", "lpav_axi_div", base + 0x78, 30); in imx8ulp_clk_pcc5_init()
501 clks[IMX8ULP_CLK_DMA2_CH30] = imx_clk_hw_gate("pcc_dma2_ch30", "lpav_axi_div", base + 0x7c, 30); in imx8ulp_clk_pcc5_init()
502 clks[IMX8ULP_CLK_DMA2_CH31] = imx_clk_hw_gate("pcc_dma2_ch31", "lpav_axi_div", base + 0x80, 30); in imx8ulp_clk_pcc5_init()
504 clks[IMX8ULP_CLK_AVD_SIM] = imx_clk_hw_gate("avd_sim", "lpav_bus_div", base + 0x94, 30); in imx8ulp_clk_pcc5_init()
506 clks[IMX8ULP_CLK_MU2_B] = imx_clk_hw_gate("mu2_b", "lpav_bus_div", base + 0x84, 30); in imx8ulp_clk_pcc5_init()
507 clks[IMX8ULP_CLK_MU3_B] = imx_clk_hw_gate("mu3_b", "lpav_bus_div", base + 0x88, 30); in imx8ulp_clk_pcc5_init()
523 clks[IMX8ULP_CLK_RGPIOD] = imx_clk_hw_gate("rgpiod", "lpav_axi_div", base + 0x114, 30); in imx8ulp_clk_pcc5_init()
526 imx_check_clk_hws(clks, clk_data->num); in imx8ulp_clk_pcc5_init()
540 probe = of_device_get_match_data(&pdev->dev); in imx8ulp_clk_probe()
549 { .compatible = "fsl,imx8ulp-pcc3", .data = imx8ulp_clk_pcc3_init },
550 { .compatible = "fsl,imx8ulp-pcc4", .data = imx8ulp_clk_pcc4_init },
551 { .compatible = "fsl,imx8ulp-pcc5", .data = imx8ulp_clk_pcc5_init },
552 { .compatible = "fsl,imx8ulp-cgc2", .data = imx8ulp_clk_cgc2_init },
553 { .compatible = "fsl,imx8ulp-cgc1", .data = imx8ulp_clk_cgc1_init },