1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
16 #include "clk-scu.h"
17 #include "clk-imx8qxp-lpcg.h"
19 #include <dt-bindings/clock/imx8-clock.h>
22  * struct imx8qxp_lpcg_data - Description of one LPCG clock
44  * struct imx8qxp_ss_lpcg - Description of one subsystem LPCG clocks
166 	unsigned int idx = clkspec->args[0] / 4;  in imx_lpcg_of_clk_src_get()
168 	if (idx >= hw_data->num) {  in imx_lpcg_of_clk_src_get()
170 		return ERR_PTR(-EINVAL);  in imx_lpcg_of_clk_src_get()
173 	return hw_data->hws[idx];  in imx_lpcg_of_clk_src_get()
190 	if (!of_device_is_compatible(np, "fsl,imx8qxp-lpcg"))  in imx_lpcg_parse_clks_from_dt()
191 		return -EINVAL;  in imx_lpcg_parse_clks_from_dt()
197 	count = of_property_count_u32_elems(np, "clock-indices");  in imx_lpcg_parse_clks_from_dt()
199 		dev_err(&pdev->dev, "failed to count clocks\n");  in imx_lpcg_parse_clks_from_dt()
200 		return -EINVAL;  in imx_lpcg_parse_clks_from_dt()
205 	 * of the count from clock-indices because one LPCG supports up to  in imx_lpcg_parse_clks_from_dt()
207 	 * easily get the clock by clk-indices (bit-offset) / 4.  in imx_lpcg_parse_clks_from_dt()
211 	clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,  in imx_lpcg_parse_clks_from_dt()
214 		return -ENOMEM;  in imx_lpcg_parse_clks_from_dt()
216 	clk_data->num = IMX_LPCG_MAX_CLKS;  in imx_lpcg_parse_clks_from_dt()
217 	clk_hws = clk_data->hws;  in imx_lpcg_parse_clks_from_dt()
219 	ret = of_property_read_u32_array(np, "clock-indices", bit_offset,  in imx_lpcg_parse_clks_from_dt()
222 		dev_err(&pdev->dev, "failed to read clock-indices\n");  in imx_lpcg_parse_clks_from_dt()
223 		return -EINVAL;  in imx_lpcg_parse_clks_from_dt()
228 		dev_err(&pdev->dev, "failed to get clock parent names\n");  in imx_lpcg_parse_clks_from_dt()
232 	ret = of_property_read_string_array(np, "clock-output-names",  in imx_lpcg_parse_clks_from_dt()
235 		dev_err(&pdev->dev, "failed to read clock-output-names\n");  in imx_lpcg_parse_clks_from_dt()
236 		return -EINVAL;  in imx_lpcg_parse_clks_from_dt()
239 	pm_runtime_get_noresume(&pdev->dev);  in imx_lpcg_parse_clks_from_dt()
240 	pm_runtime_set_active(&pdev->dev);  in imx_lpcg_parse_clks_from_dt()
241 	pm_runtime_set_autosuspend_delay(&pdev->dev, 500);  in imx_lpcg_parse_clks_from_dt()
242 	pm_runtime_use_autosuspend(&pdev->dev);  in imx_lpcg_parse_clks_from_dt()
243 	pm_runtime_enable(&pdev->dev);  in imx_lpcg_parse_clks_from_dt()
248 			dev_warn(&pdev->dev, "invalid bit offset of clock %d\n",  in imx_lpcg_parse_clks_from_dt()
250 			ret = -EINVAL;  in imx_lpcg_parse_clks_from_dt()
254 		clk_hws[idx] = imx_clk_lpcg_scu_dev(&pdev->dev, output_names[i],  in imx_lpcg_parse_clks_from_dt()
258 			dev_warn(&pdev->dev, "failed to register clock %d\n",  in imx_lpcg_parse_clks_from_dt()
265 	ret = devm_of_clk_add_hw_provider(&pdev->dev, imx_lpcg_of_clk_src_get,  in imx_lpcg_parse_clks_from_dt()
270 	pm_runtime_mark_last_busy(&pdev->dev);  in imx_lpcg_parse_clks_from_dt()
271 	pm_runtime_put_autosuspend(&pdev->dev);  in imx_lpcg_parse_clks_from_dt()
276 	while (--i >= 0) {  in imx_lpcg_parse_clks_from_dt()
282 	pm_runtime_disable(&pdev->dev);  in imx_lpcg_parse_clks_from_dt()
289 	struct device *dev = &pdev->dev;  in imx8qxp_lpcg_clk_probe()
290 	struct device_node *np = dev->of_node;  in imx8qxp_lpcg_clk_probe()
307 		return -ENODEV;  in imx8qxp_lpcg_clk_probe()
322 		return -EINVAL;  in imx8qxp_lpcg_clk_probe()
323 	base = devm_ioremap(dev, res->start, resource_size(res));  in imx8qxp_lpcg_clk_probe()
325 		return -ENOMEM;  in imx8qxp_lpcg_clk_probe()
327 	clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,  in imx8qxp_lpcg_clk_probe()
328 				ss_lpcg->num_max), GFP_KERNEL);  in imx8qxp_lpcg_clk_probe()
330 		return -ENOMEM;  in imx8qxp_lpcg_clk_probe()
332 	clk_data->num = ss_lpcg->num_max;  in imx8qxp_lpcg_clk_probe()
333 	clks = clk_data->hws;  in imx8qxp_lpcg_clk_probe()
335 	for (i = 0; i < ss_lpcg->num_lpcg; i++) {  in imx8qxp_lpcg_clk_probe()
336 		lpcg = ss_lpcg->lpcg + i;  in imx8qxp_lpcg_clk_probe()
337 		clks[lpcg->id] = imx_clk_lpcg_scu(lpcg->name, lpcg->parent,  in imx8qxp_lpcg_clk_probe()
338 						  lpcg->flags, base + lpcg->offset,  in imx8qxp_lpcg_clk_probe()
339 						  lpcg->bit_idx, lpcg->hw_gate);  in imx8qxp_lpcg_clk_probe()
342 	for (i = 0; i < clk_data->num; i++) {  in imx8qxp_lpcg_clk_probe()
344 			pr_warn("i.MX clk %u: register failed with %ld\n",  in imx8qxp_lpcg_clk_probe()
352 	{ .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, },
353 	{ .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
354 	{ .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
355 	{ .compatible = "fsl,imx8qxp-lpcg", NULL },
361 		.name = "imx8qxp-lpcg-clk",