1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <linux/clk-provider.h>
65 	"ecspi_root", "dummy", "usdhc3", "pcie", "arm", "csi_core",
131 	clk_hw_data->num = IMX6SX_CLK_CLK_END;  in imx6sx_clocks_init()
132 	hws = clk_hw_data->hws;  in imx6sx_clocks_init()
147 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");  in imx6sx_clocks_init()
178 	clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk);  in imx6sx_clocks_init()
179 	clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk);  in imx6sx_clocks_init()
180 	clk_set_parent(hws[IMX6SX_PLL3_BYPASS]->clk, hws[IMX6SX_CLK_PLL3]->clk);  in imx6sx_clocks_init()
181 	clk_set_parent(hws[IMX6SX_PLL4_BYPASS]->clk, hws[IMX6SX_CLK_PLL4]->clk);  in imx6sx_clocks_init()
182 	clk_set_parent(hws[IMX6SX_PLL5_BYPASS]->clk, hws[IMX6SX_CLK_PLL5]->clk);  in imx6sx_clocks_init()
183 	clk_set_parent(hws[IMX6SX_PLL6_BYPASS]->clk, hws[IMX6SX_CLK_PLL6]->clk);  in imx6sx_clocks_init()
184 	clk_set_parent(hws[IMX6SX_PLL7_BYPASS]->clk, hws[IMX6SX_CLK_PLL7]->clk);  in imx6sx_clocks_init()
195 	 * Bit 20 is the reserved and read-only bit, we do this only for:  in imx6sx_clocks_init()
196 	 * - Do nothing for usbphy clk_enable/disable  in imx6sx_clocks_init()
197 	 * - Keep refcount when do usbphy clk_enable/disable, in that case,  in imx6sx_clocks_init()
210 	/* FIXME 100MHz is used for pcie ref for all imx6 pcie, excepted imx6q */  in imx6sx_clocks_init()
494 		clk_prepare_enable(hws[IMX6SX_CLK_USBPHY1_GATE]->clk);  in imx6sx_clocks_init()
495 		clk_prepare_enable(hws[IMX6SX_CLK_USBPHY2_GATE]->clk);  in imx6sx_clocks_init()
499 	clk_set_parent(hws[IMX6SX_CLK_EIM_SLOW_SEL]->clk, hws[IMX6SX_CLK_PLL2_PFD2]->clk);  in imx6sx_clocks_init()
500 	clk_set_rate(hws[IMX6SX_CLK_EIM_SLOW]->clk, 132000000);  in imx6sx_clocks_init()
502 	np = of_find_node_by_path("/soc/bus@2200000/spba-bus@2240000/lcdif@2220000");  in imx6sx_clocks_init()
503 	lcdif1_assigned_clk = of_find_property(np, "assigned-clock-parents", NULL);  in imx6sx_clocks_init()
507 		clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk,  in imx6sx_clocks_init()
508 			       hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk);  in imx6sx_clocks_init()
509 		clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk,  in imx6sx_clocks_init()
510 			       hws[IMX6SX_CLK_LCDIF1_PODF]->clk);  in imx6sx_clocks_init()
513 	/* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */  in imx6sx_clocks_init()
514 	if (clk_set_parent(hws[IMX6SX_CLK_LVDS1_SEL]->clk, hws[IMX6SX_CLK_PCIE_REF_125M]->clk))  in imx6sx_clocks_init()
515 		pr_err("Failed to set pcie bus parent clk.\n");  in imx6sx_clocks_init()
519 	 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB  in imx6sx_clocks_init()
521 	clk_set_parent(hws[IMX6SX_CLK_ENET_PRE_SEL]->clk, hws[IMX6SX_CLK_PLL2_PFD2]->clk);  in imx6sx_clocks_init()
522 	clk_set_parent(hws[IMX6SX_CLK_ENET_SEL]->clk, hws[IMX6SX_CLK_ENET_PODF]->clk);  in imx6sx_clocks_init()
523 	clk_set_rate(hws[IMX6SX_CLK_ENET_PODF]->clk, 200000000);  in imx6sx_clocks_init()
524 	clk_set_rate(hws[IMX6SX_CLK_ENET_REF]->clk, 125000000);  in imx6sx_clocks_init()
525 	clk_set_rate(hws[IMX6SX_CLK_ENET2_REF]->clk, 125000000);  in imx6sx_clocks_init()
528 	clk_set_rate(hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk, 393216000);  in imx6sx_clocks_init()
530 	clk_set_parent(hws[IMX6SX_CLK_SPDIF_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);  in imx6sx_clocks_init()
531 	clk_set_rate(hws[IMX6SX_CLK_SPDIF_PODF]->clk, 98304000);  in imx6sx_clocks_init()
533 	clk_set_parent(hws[IMX6SX_CLK_AUDIO_SEL]->clk, hws[IMX6SX_CLK_PLL3_USB_OTG]->clk);  in imx6sx_clocks_init()
534 	clk_set_rate(hws[IMX6SX_CLK_AUDIO_PODF]->clk, 24000000);  in imx6sx_clocks_init()
536 	clk_set_parent(hws[IMX6SX_CLK_SSI1_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);  in imx6sx_clocks_init()
537 	clk_set_parent(hws[IMX6SX_CLK_SSI2_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);  in imx6sx_clocks_init()
538 	clk_set_parent(hws[IMX6SX_CLK_SSI3_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);  in imx6sx_clocks_init()
539 	clk_set_rate(hws[IMX6SX_CLK_SSI1_PODF]->clk, 24576000);  in imx6sx_clocks_init()
540 	clk_set_rate(hws[IMX6SX_CLK_SSI2_PODF]->clk, 24576000);  in imx6sx_clocks_init()
541 	clk_set_rate(hws[IMX6SX_CLK_SSI3_PODF]->clk, 24576000);  in imx6sx_clocks_init()
543 	clk_set_parent(hws[IMX6SX_CLK_ESAI_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk);  in imx6sx_clocks_init()
544 	clk_set_rate(hws[IMX6SX_CLK_ESAI_PODF]->clk, 24576000);  in imx6sx_clocks_init()
547 	clk_set_parent(hws[IMX6SX_CLK_VID_SEL]->clk, hws[IMX6SX_CLK_PLL3_USB_OTG]->clk);  in imx6sx_clocks_init()
550 	clk_set_parent(hws[IMX6SX_CLK_CAN_SEL]->clk, hws[IMX6SX_CLK_PLL3_60M]->clk);  in imx6sx_clocks_init()
553 	clk_set_parent(hws[IMX6SX_CLK_GPU_CORE_SEL]->clk, hws[IMX6SX_CLK_PLL3_PFD0]->clk);  in imx6sx_clocks_init()
554 	clk_set_parent(hws[IMX6SX_CLK_GPU_AXI_SEL]->clk, hws[IMX6SX_CLK_PLL3_PFD0]->clk);  in imx6sx_clocks_init()
556 	clk_set_parent(hws[IMX6SX_CLK_QSPI1_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk);  in imx6sx_clocks_init()
557 	clk_set_parent(hws[IMX6SX_CLK_QSPI2_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk);  in imx6sx_clocks_init()
561 CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);