Lines Matching +full:imx6sll +full:- +full:ccm

1 // SPDX-License-Identifier: GPL-2.0
4  * Copyright 2017-2018 NXP.
7 #include <dt-bindings/clock/imx6sll-clock.h>
10 #include <linux/clk-provider.h>
89 	clk_hw_data->num = IMX6SLL_CLK_END;  in imx6sll_clocks_init()
90 	hws = clk_hw_data->hws;  in imx6sll_clocks_init()
101 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop");  in imx6sll_clocks_init()
148 	 * Bit 20 is the reserved and read-only bit, we do this only for:  in imx6sll_clocks_init()
149 	 * - Do nothing for usbphy clk_enable/disable  in imx6sll_clocks_init()
150 	 * - Keep refcount when do usbphy clk_enable/disable, in that case,  in imx6sll_clocks_init()
346 	clk_set_rate(hws[IMX6SLL_CLK_AHB]->clk, 99000000);  in imx6sll_clocks_init()
349 	clk_set_parent(hws[IMX6SLL_CLK_PERIPH_CLK2_SEL]->clk, hws[IMX6SLL_CLK_PLL3_USB_OTG]->clk);  in imx6sll_clocks_init()
350 	clk_set_parent(hws[IMX6SLL_CLK_PERIPH]->clk, hws[IMX6SLL_CLK_PERIPH_CLK2]->clk);  in imx6sll_clocks_init()
351 	clk_set_parent(hws[IMX6SLL_CLK_PERIPH_PRE]->clk, hws[IMX6SLL_CLK_PLL2_BUS]->clk);  in imx6sll_clocks_init()
352 	clk_set_parent(hws[IMX6SLL_CLK_PERIPH]->clk, hws[IMX6SLL_CLK_PERIPH_PRE]->clk);  in imx6sll_clocks_init()
354 	clk_set_rate(hws[IMX6SLL_CLK_AHB]->clk, 132000000);  in imx6sll_clocks_init()
356 CLK_OF_DECLARE_DRIVER(imx6sll, "fsl,imx6sll-ccm", imx6sll_clocks_init);