Lines Matching +full:imx6q +full:- +full:usbphy
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/clk-provider.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <dt-bindings/clock/imx6qdl-clock.h>
135 return of_machine_is_compatible("fsl,imx6q"); in clk_on_imx6q()
154 return -ENOENT; in ldb_di_sel_by_clock_id()
165 return -ENOENT; in ldb_di_sel_by_clock_id()
177 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in of_assigned_ldb_sels()
178 "#clock-cells"); in of_assigned_ldb_sels()
180 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in of_assigned_ldb_sels()
181 "#clock-cells", index, &clkspec); in of_assigned_ldb_sels()
184 if (rc == -ENOENT) in of_assigned_ldb_sels()
195 rc = of_parse_phandle_with_args(node, "assigned-clocks", in of_assigned_ldb_sels()
196 "#clock-cells", index, &clkspec); in of_assigned_ldb_sels()
228 num_clocks = of_count_phandle_with_args(node, "assigned-clocks", in pll6_bypassed()
229 "#clock-cells"); in pll6_bypassed()
234 ret = of_parse_phandle_with_args(node, "assigned-clocks", in pll6_bypassed()
235 "#clock-cells", index, in pll6_bypassed()
249 ret = of_parse_phandle_with_args(node, "assigned-clock-parents", in pll6_bypassed()
250 "#clock-cells", index, &clkspec); in pll6_bypassed()
275 clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk, in mmdc_ch1_disable()
276 hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); in mmdc_ch1_disable()
306 * to decide between the first and second 4-port mux:
308 * pll5_video_div 0 --|\
309 * pll2_pfd0_352m 1 --| |_
310 * pll2_pfd2_396m 2 --| | `-|\
311 * mmdc_ch1_axi 3 --|/ | |
312 * | |--
313 * pll3_usb_otg 4 --|\ | |
314 * 5 --| |_,-|/
315 * 6 --| |
316 * 7 --|/
318 * The ldb_di0/1_clk_sel[1:0] bits control both 4-port muxes at the same time.
319 * The ldb_di0/1_clk_sel[2] bit controls the 2-port mux. The code below
350 (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == in init_ldb_clks()
351 hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)) { in init_ldb_clks()
364 pr_debug("ccm: switching ldb_di%d_sel: %d->%d->%d->%d\n", i, in init_ldb_clks()
400 /* Make sure PLL2 PFDs 0-2 are gated */ in disable_anatop_clocks()
403 if (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == in disable_anatop_clocks()
404 hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk) in disable_anatop_clocks()
410 /* Make sure PLL3 PFDs 0-3 are gated */ in disable_anatop_clocks()
447 clk_hw_data->num = IMX6QDL_CLK_END; in imx6q_clocks_init()
448 hws = clk_hw_data->hws; in imx6q_clocks_init()
460 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); in imx6q_clocks_init()
499 clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk); in imx6q_clocks_init()
500 clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk); in imx6q_clocks_init()
501 clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk); in imx6q_clocks_init()
502 clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk); in imx6q_clocks_init()
503 clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk); in imx6q_clocks_init()
504 clk_set_parent(hws[IMX6QDL_PLL6_BYPASS]->clk, hws[IMX6QDL_CLK_PLL6]->clk); in imx6q_clocks_init()
505 clk_set_parent(hws[IMX6QDL_PLL7_BYPASS]->clk, hws[IMX6QDL_CLK_PLL7]->clk); in imx6q_clocks_init()
516 * Bit 20 is the reserved and read-only bit, we do this only for: in imx6q_clocks_init()
517 * - Do nothing for usbphy clk_enable/disable in imx6q_clocks_init()
518 * - Keep refcount when do usbphy clk_enable/disable, in that case, in imx6q_clocks_init()
519 * the clk framework may need to enable/disable usbphy's parent in imx6q_clocks_init()
525 * usbphy*_gate needs to be on after system boots up, and software in imx6q_clocks_init()
533 * different post-dividers that are all affected by the single bypass in imx6q_clocks_init()
561 * lvds1_gate and lvds2_gate are pseudo-gates. Both can be in imx6q_clocks_init()
653 * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware in imx6q_clocks_init()
853 * The multiplexer and divider of the imx6q clock gpu2d get in imx6q_clocks_init()
918 hws[IMX6QDL_CLK_ENET_REF_SEL] = imx_clk_gpr_mux("enet_ref_sel", "fsl,imx6q-iomuxc-gpr", in imx6q_clocks_init()
928 clk_set_rate(hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk, 540000000); in imx6q_clocks_init()
930 clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk); in imx6q_clocks_init()
932 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()
933 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()
934 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()
935 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()
936 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI0_PRE]->clk); in imx6q_clocks_init()
937 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI1_PRE]->clk); in imx6q_clocks_init()
938 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI0_PRE]->clk); in imx6q_clocks_init()
939 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI1_PRE]->clk); in imx6q_clocks_init()
946 clk_set_parent(hws[IMX6QDL_CLK_ENFC_SEL]->clk, hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk); in imx6q_clocks_init()
949 clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY1_GATE]->clk); in imx6q_clocks_init()
950 clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY2_GATE]->clk); in imx6q_clocks_init()
955 * is widely used by imx6q board designs to clock audio codec. in imx6q_clocks_init()
957 ret = clk_set_parent(hws[IMX6QDL_CLK_CKO2_SEL]->clk, hws[IMX6QDL_CLK_OSC]->clk); in imx6q_clocks_init()
959 ret = clk_set_parent(hws[IMX6QDL_CLK_CKO]->clk, hws[IMX6QDL_CLK_CKO2]->clk); in imx6q_clocks_init()
963 /* Audio-related clocks configuration */ in imx6q_clocks_init()
964 clk_set_parent(hws[IMX6QDL_CLK_SPDIF_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD3_454M]->clk); in imx6q_clocks_init()
968 clk_set_parent(hws[IMX6QDL_CLK_LVDS1_SEL]->clk, hws[IMX6QDL_CLK_SATA_REF_100M]->clk); in imx6q_clocks_init()
975 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk, in imx6q_clocks_init()
976 hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk); in imx6q_clocks_init()
977 clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk, in imx6q_clocks_init()
978 hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk); in imx6q_clocks_init()
980 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk, in imx6q_clocks_init()
981 hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk); in imx6q_clocks_init()
982 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_SHADER_SEL]->clk, in imx6q_clocks_init()
983 hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk); in imx6q_clocks_init()
984 clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk, in imx6q_clocks_init()
985 hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); in imx6q_clocks_init()
988 clk_set_parent(hws[IMX6QDL_CLK_ENET_REF_SEL]->clk, hws[IMX6QDL_CLK_ENET_REF]->clk); in imx6q_clocks_init()
992 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);