Lines Matching +full:pll +full:-

1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
125 imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate)
127 	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
130 	for (i = 0; i < pll->rate_count; i++)
140 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
141 	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
145 	for (i = 0; i < pll->rate_count; i++)
146 		if (req->rate >= rate_table[i].rate) {
147 			req->rate = rate_table[i].rate;
153 	req->rate = rate_table[pll->rate_count - 1].rate;
160 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
161 	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
168 	pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR);
171 	pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR);
174 	pll_div = readl_relaxed(pll->base + PLL_DIV);
182 	 * the frac part. So find the accurate pll rate from the table
186 	for (i = 0; i < pll->rate_count; i++) {
210 	if (pll->flags & CLK_FRACN_GPPLL_INTEGER) {
223 static int clk_fracn_gppll_wait_lock(struct clk_fracn_gppll *pll)
227 	return readl_poll_timeout(pll->base + PLL_STATUS, val,
234 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
239 	rate = imx_get_pll_settings(pll, drate);
241 	/* Hardware control select disable. PLL is control by register */
242 	tmp = readl_relaxed(pll->base + PLL_CTRL);
244 	writel_relaxed(tmp, pll->base + PLL_CTRL);
247 	tmp = readl_relaxed(pll->base + PLL_CTRL);
249 	writel_relaxed(tmp, pll->base + PLL_CTRL);
253 	writel_relaxed(tmp, pll->base + PLL_CTRL);
257 	writel_relaxed(tmp, pll->base + PLL_CTRL);
259 	pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv |
260 		FIELD_PREP(PLL_MFI_MASK, rate->mfi);
261 	writel_relaxed(pll_div, pll->base + PLL_DIV);
262 	readl(pll->base + PLL_DIV);
263 	if (pll->flags & CLK_FRACN_GPPLL_FRACN) {
264 		writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);
265 		writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);
266 		readl(pll->base + PLL_NUMERATOR);
269 	/* Wait for 5us according to fracn mode pll doc */
274 	writel_relaxed(tmp, pll->base + PLL_CTRL);
275 	readl(pll->base + PLL_CTRL);
278 	ret = clk_fracn_gppll_wait_lock(pll);
284 	writel_relaxed(tmp, pll->base + PLL_CTRL);
286 	ana_mfn = readl_relaxed(pll->base + PLL_STATUS);
289 	WARN(ana_mfn != rate->mfn, "ana_mfn != rate->mfn\n");
296 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
300 	val = readl_relaxed(pll->base + PLL_CTRL);
304 	if (pll->flags & CLK_FRACN_GPPLL_FRACN)
305 		writel_relaxed(readl_relaxed(pll->base + PLL_NUMERATOR),
306 			       pll->base + PLL_NUMERATOR);
309 	writel_relaxed(val, pll->base + PLL_CTRL);
312 	writel_relaxed(val, pll->base + PLL_CTRL);
313 	readl(pll->base + PLL_CTRL);
315 	ret = clk_fracn_gppll_wait_lock(pll);
320 	writel_relaxed(val, pll->base + PLL_CTRL);
323 	writel_relaxed(val, pll->base + PLL_CTRL);
330 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
333 	val = readl_relaxed(pll->base + PLL_CTRL);
340 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
343 	val = readl_relaxed(pll->base + PLL_CTRL);
345 	writel_relaxed(val, pll->base + PLL_CTRL);
362 	struct clk_fracn_gppll *pll;
367 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
368 	if (!pll)
369 		return ERR_PTR(-ENOMEM);
372 	init.flags = pll_clk->flags;
377 	pll->base = base;
378 	pll->hw.init = &init;
379 	pll->rate_table = pll_clk->rate_table;
380 	pll->rate_count = pll_clk->rate_count;
381 	pll->flags = pll_flags;
383 	hw = &pll->hw;
387 		pr_err("%s: failed to register pll %s %d\n", __func__, name, ret);
388 		kfree(pll);