1 // SPDX-License-Identifier: GPL-2.0
5  * This driver supports the fractional plls found in the imx8m SOCs
8  *   https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
11 #include <linux/clk-provider.h>
48 	return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0,  in clk_wait_lock()
57 	if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK))  in clk_wait_ack()
61 	return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0,  in clk_wait_ack()
70 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_pll_prepare()
72 	writel_relaxed(val, pll->base + PLL_CFG0);  in clk_pll_prepare()
82 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_pll_unprepare()
84 	writel_relaxed(val, pll->base + PLL_CFG0);  in clk_pll_unprepare()
92 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_pll_is_prepared()
104 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_pll_recalc_rate()
106 	val = readl_relaxed(pll->base + PLL_CFG1);  in clk_pll_recalc_rate()
134 	temp64 = rate - divfi * parent_rate;  in clk_pll_round_rate()
149  * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero
167 	temp64 = rate - temp64;  in clk_pll_set_rate()
172 	val = readl_relaxed(pll->base + PLL_CFG1);  in clk_pll_set_rate()
174 	val |= (divff << 7) | (divfi - 1);  in clk_pll_set_rate()
175 	writel_relaxed(val, pll->base + PLL_CFG1);  in clk_pll_set_rate()
177 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_pll_set_rate()
179 	writel_relaxed(val, pll->base + PLL_CFG0);  in clk_pll_set_rate()
182 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_pll_set_rate()
184 	writel_relaxed(val, pll->base + PLL_CFG0);  in clk_pll_set_rate()
189 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_pll_set_rate()
191 	writel_relaxed(val, pll->base + PLL_CFG0);  in clk_pll_set_rate()
216 		return ERR_PTR(-ENOMEM);  in imx_clk_hw_frac_pll()
224 	pll->base = base;  in imx_clk_hw_frac_pll()
225 	pll->hw.init = &init;  in imx_clk_hw_frac_pll()
227 	hw = &pll->hw;  in imx_clk_hw_frac_pll()