Lines Matching +full:reg +full:- +full:mux

1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
36 	prediv_value = readl(divider->reg) >> divider->shift;
37 	prediv_value &= clk_div_mask(divider->width);
40 						NULL, divider->flags,
41 						divider->width);
43 	div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
47 				   divider->flags, PCG_DIV_WIDTH);
56 	int ret = -EINVAL;
63 			int new_error = ((parent_rate / div1) / div2) - rate;
90 		return -EINVAL;
92 	spin_lock_irqsave(divider->lock, flags);
94 	orig = readl(divider->reg);
95 	val = orig & ~((clk_div_mask(divider->width) << divider->shift) |
98 	val |= (u32)(prediv_value  - 1) << divider->shift;
99 	val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
102 		writel(val, divider->reg);
104 	spin_unlock_irqrestore(divider->lock, flags);
117 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {
120 		val = readl(divider->reg);
121 		prediv_value = val >> divider->shift;
122 		prediv_value &= clk_div_mask(divider->width);
129 		return divider_ro_determine_rate(hw, req, divider->table,
131 						 divider->flags, prediv_value * div_value);
134 	return divider_determine_rate(hw, req, divider->table,
136 				      divider->flags);
152 	struct clk_mux *mux = to_clk_mux(hw);
153 	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
155 	u32 reg;
157 	if (mux->lock)
158 		spin_lock_irqsave(mux->lock, flags);
160 	reg = readl(mux->reg);
161 	reg &= ~(mux->mask << mux->shift);
162 	val = val << mux->shift;
163 	reg |= val;
165 	 * write twice to make sure non-target interface
168 	writel(reg, mux->reg);
169 	writel(reg, mux->reg);
171 	if (mux->lock)
172 		spin_unlock_irqrestore(mux->lock, flags);
197 	spin_lock_irqsave(gate->lock, flags);
199 	val = readl(gate->reg);
200 	val |= BIT(gate->bit_idx);
201 	writel(val, gate->reg);
203 	spin_unlock_irqrestore(gate->lock, flags);
221 					int num_parents, void __iomem *reg,
225 	struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
229 	struct clk_mux *mux;
234 	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
235 	if (!mux)
238 	mux_hw = &mux->hw;
239 	mux->reg = reg;
240 	mux->shift = PCG_PCS_SHIFT;
241 	mux->mask = PCG_PCS_MASK;
242 	mux->lock = &imx_ccm_lock;
248 	div_hw = &div->hw;
249 	div->reg = reg;
251 		div->shift = PCG_DIV_SHIFT;
252 		div->width = PCG_CORE_DIV_WIDTH;
256 		div->shift = PCG_PREDIV_SHIFT;
257 		div->width = PCG_PREDIV_WIDTH;
261 		div->shift = PCG_PREDIV_SHIFT;
262 		div->width = PCG_PREDIV_WIDTH;
269 	div->lock = &imx_ccm_lock;
270 	div->flags = CLK_DIVIDER_ROUND_CLOSEST;
277 	gate_hw = &gate->hw;
278 	gate->reg = reg;
279 	gate->bit_idx = PCG_CGC_SHIFT;
280 	gate->lock = &imx_ccm_lock;
299 	kfree(mux);