Lines Matching +full:100 +full:m

48 	{ HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
49 	{ HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
50 	{ HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
51 	{ HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
52 	{ HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
53 	{ HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
54 	{ HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
55 	{ HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
56 	{ HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
58 	{ HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
59 	{ HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, },
63 		"100m", "50m", "25m", "200m", "150m" };
67 		"100m", "25m"};
71 		"100m", "50m", "150m", "166p5m" };
102 	{ HISTB_UART2_CLK, "clk_uart2", "75m",
119 	{ HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m",
124 	{ HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m",
129 	{ HISTB_PCIE_BUS_CLK, "clk_pcie_bus", "200m",
131 	{ HISTB_PCIE_SYS_CLK, "clk_pcie_sys", "100m",
133 	{ HISTB_PCIE_PIPE_CLK, "clk_pcie_pipe", "250m",
135 	{ HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m",
163 	{ HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m",
165 	{ HISTB_USB2_12M_CLK, "clk_u2_12m", "12m",
167 	{ HISTB_USB2_48M_CLK, "clk_u2_48m", "48m",
169 	{ HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m",
171 	{ HISTB_USB2_OTG_UTMI_CLK, "clk_u2_otg_utmi", "60m",
173 	{ HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m",
175 	{ HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
281 	{ HISTB_IR_CLK, "clk_ir", "24m",
283 	{ HISTB_TIMER01_CLK, "clk_timer01", "24m",
285 	{ HISTB_UART0_CLK, "clk_uart0", "75m",