1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
33 /* CPU dynamic frequency scaling */
71 	regmap_read(stub_clk->dfs_map, ACPU_DFS_CUR_FREQ, &freq);  in hi6220_acpu_get_freq()
80 	/* set the frequency in sram */  in hi6220_acpu_set_freq()
81 	regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, freq);  in hi6220_acpu_set_freq()
89 	mbox_send_message(stub_clk->mbox, &data);  in hi6220_acpu_set_freq()
99 	/* check the constrained frequency */  in hi6220_acpu_round_freq()
100 	regmap_read(stub_clk->dfs_map, ACPU_DFS_FLAG, &limit_flag);  in hi6220_acpu_round_freq()
102 		regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, &limit_freq);  in hi6220_acpu_round_freq()
104 	/* check the supported maximum frequency */  in hi6220_acpu_round_freq()
105 	regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_MAX, &max_freq);  in hi6220_acpu_round_freq()
107 	/* calculate the real maximum frequency */  in hi6220_acpu_round_freq()
122 	switch (stub_clk->id) {  in hi6220_stub_clk_recalc_rate()
126 		/* convert from kHz to Hz */  in hi6220_stub_clk_recalc_rate()
131 		dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",  in hi6220_stub_clk_recalc_rate()
132 			__func__, stub_clk->id);  in hi6220_stub_clk_recalc_rate()
146 	switch (stub_clk->id) {  in hi6220_stub_clk_set_rate()
155 		dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",  in hi6220_stub_clk_set_rate()
156 			__func__, stub_clk->id);  in hi6220_stub_clk_set_rate()
170 	switch (stub_clk->id) {  in hi6220_stub_clk_round_rate()
174 		/* convert from kHz to Hz */  in hi6220_stub_clk_round_rate()
179 		dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",  in hi6220_stub_clk_round_rate()
180 			__func__, stub_clk->id);  in hi6220_stub_clk_round_rate()
195 	struct device *dev = &pdev->dev;  in hi6220_stub_clk_probe()
199 	struct device_node *np = pdev->dev.of_node;  in hi6220_stub_clk_probe()
204 		return -ENOMEM;  in hi6220_stub_clk_probe()
206 	stub_clk->dfs_map = syscon_regmap_lookup_by_phandle(np,  in hi6220_stub_clk_probe()
207 				"hisilicon,hi6220-clk-sram");  in hi6220_stub_clk_probe()
208 	if (IS_ERR(stub_clk->dfs_map)) {  in hi6220_stub_clk_probe()
210 		return PTR_ERR(stub_clk->dfs_map);  in hi6220_stub_clk_probe()
213 	stub_clk->hw.init = &init;  in hi6220_stub_clk_probe()
214 	stub_clk->dev = dev;  in hi6220_stub_clk_probe()
215 	stub_clk->id = HI6220_STUB_ACPU0;  in hi6220_stub_clk_probe()
218 	stub_clk->cl.dev = dev;  in hi6220_stub_clk_probe()
219 	stub_clk->cl.tx_done = NULL;  in hi6220_stub_clk_probe()
220 	stub_clk->cl.tx_block = true;  in hi6220_stub_clk_probe()
221 	stub_clk->cl.tx_tout = 500;  in hi6220_stub_clk_probe()
222 	stub_clk->cl.knows_txdone = false;  in hi6220_stub_clk_probe()
225 	stub_clk->mbox = mbox_request_channel(&stub_clk->cl, 0);  in hi6220_stub_clk_probe()
226 	if (IS_ERR(stub_clk->mbox)) {  in hi6220_stub_clk_probe()
228 		return PTR_ERR(stub_clk->mbox);  in hi6220_stub_clk_probe()
236 	clk = devm_clk_register(dev, &stub_clk->hw);  in hi6220_stub_clk_probe()
247 	regmap_write(stub_clk->dfs_map, ACPU_DFS_FLAG, 0x0);  in hi6220_stub_clk_probe()
248 	regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, 0x0);  in hi6220_stub_clk_probe()
249 	regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, 0x0);  in hi6220_stub_clk_probe()
256 	{ .compatible = "hisilicon,hi6220-stub-clk", },
262 		.name = "hi6220-stub-clk",